mirror of
https://github.com/MCKero6423/uv-k5-v3-emulator.git
synced 2026-10-02 03:15:36 +00:00
mckero
c0a09827ed
Adds a QEMU machine for the Puya PY32F071 (Cortex-M0+) so Quansheng UV-K5 V3 firmware can run on a PC. The firmware boots to its main loop in about five seconds and the LCD contents are readable. Register layouts come from the vendor CMSIS header shipped with the firmware rather than guesswork. Modelled: RCC, GPIO, ADC, both SPI controllers, DMA1 and the PY25Q16 flash; everything else answers through a logging catch-all, which is how the next thing worth modelling gets identified. Seven things had to be right before it would boot, each found by watching where the firmware stopped: flash aliased at the application offset, clock ready bits, self-clearing ADC calibration, SPI transfer flags, DMA-driven flash reads, SysTick poll acceleration, and the bit-banged transceiver bus idling low. SysTick needs explanation. SYSTICK_DelayUs polls the counter and accumulates differences; under emulation a register read costs far more relative to guest time, so a measured 120 ms delay would have taken about 7.7 hours. Lowering the clock does not help because the bottleneck is loop iterations, not counter speed. Reporting a value that runs ahead of the real counter does, via a new poll-boost property on SysTick. Guest time therefore runs fast during delays: fine for exercising menus and control flow, wrong for judging signal timing. Also includes the host build of the CW timing chain (harness, stubs, shim, tests), which compiles app/cwkeyer.c and app/cwmacro.c unmodified against stub drivers with a virtual clock and scripted paddle input. Known gap: keypad rows reach the firmware's scan and KEYBOARD_Poll returns the right key code, but the UI does not react yet. Not modelled, and not intended to be: radio behaviour. The transceiver chip has no public datasheet, so keying envelopes and emissions need real hardware.
100 lines
3.4 KiB
C
100 lines
3.4 KiB
C
/* Minimal stand-in for the PY32 GPIO LL header.
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*
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* driver/gpio.h names GPIO port pointers and LL_GPIO_PIN_* constants at file
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* scope, so those have to exist for the firmware headers to parse. Nothing here
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* touches real hardware: the ports are dummy objects and the pin masks only need
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* to be distinct, because the simulator resolves key state through the scripted
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* paddle timeline instead of reading pins.
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*/
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#ifndef PY32F071_LL_GPIO_H_SHIM
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#define PY32F071_LL_GPIO_H_SHIM
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#include <stdint.h>
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typedef struct {
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volatile uint32_t MODER;
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volatile uint32_t OTYPER;
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volatile uint32_t OSPEEDR;
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volatile uint32_t PUPDR;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile uint32_t BSRR;
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volatile uint32_t LCKR;
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volatile uint32_t AFR[2];
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volatile uint32_t BRR;
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} GPIO_TypeDef;
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// The firmware treats these as numeric addresses: driver/gpio.h packs a port
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// into the high half of a pin id (GPIO_MAKE_PIN) inside an enum, so they must be
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// integer constant expressions, and GPIO_PORT() casts them back to a pointer.
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// Keep that shape -- the accessors below resolve the fake address to real
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// storage instead of dereferencing it, so no host memory at 0x0000 is touched.
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#define IOPORT_BASE 0u
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#define GPIOA 0x0000u
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#define GPIOB 0x0100u
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#define GPIOC 0x0200u
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#define GPIOF 0x0300u
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// Resolves a fake port address to backing storage. Defined in
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// stubs/firmware_globals.c.
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GPIO_TypeDef *SIM_GpioPort(void *fake_address);
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#define LL_GPIO_PIN_0 (1u << 0)
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#define LL_GPIO_PIN_1 (1u << 1)
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#define LL_GPIO_PIN_2 (1u << 2)
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#define LL_GPIO_PIN_3 (1u << 3)
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#define LL_GPIO_PIN_4 (1u << 4)
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#define LL_GPIO_PIN_5 (1u << 5)
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#define LL_GPIO_PIN_6 (1u << 6)
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#define LL_GPIO_PIN_7 (1u << 7)
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#define LL_GPIO_PIN_8 (1u << 8)
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#define LL_GPIO_PIN_9 (1u << 9)
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#define LL_GPIO_PIN_10 (1u << 10)
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#define LL_GPIO_PIN_11 (1u << 11)
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#define LL_GPIO_PIN_12 (1u << 12)
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#define LL_GPIO_PIN_13 (1u << 13)
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#define LL_GPIO_PIN_14 (1u << 14)
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#define LL_GPIO_PIN_15 (1u << 15)
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#define LL_GPIO_MODE_INPUT 0u
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#define LL_GPIO_MODE_OUTPUT 1u
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#define LL_GPIO_MODE_ALTERNATE 2u
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#define LL_GPIO_MODE_ANALOG 3u
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#define LL_GPIO_PULL_NO 0u
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#define LL_GPIO_PULL_UP 1u
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#define LL_GPIO_PULL_DOWN 2u
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#define LL_GPIO_OUTPUT_PUSHPULL 0u
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#define LL_GPIO_OUTPUT_OPENDRAIN 1u
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#define LL_GPIO_SPEED_FREQ_LOW 0u
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#define LL_GPIO_SPEED_FREQ_MEDIUM 1u
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#define LL_GPIO_SPEED_FREQ_HIGH 2u
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#define LL_GPIO_SPEED_FREQ_VERY_HIGH 3u
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static inline uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *port, uint32_t pin)
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{
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return (SIM_GpioPort(port)->IDR & pin) ? 1u : 0u;
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}
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static inline void LL_GPIO_SetOutputPin(GPIO_TypeDef *port, uint32_t pin)
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{
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SIM_GpioPort(port)->ODR |= pin;
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}
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static inline void LL_GPIO_ResetOutputPin(GPIO_TypeDef *port, uint32_t pin)
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{
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SIM_GpioPort(port)->ODR &= ~pin;
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}
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static inline uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *port, uint32_t pin)
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{
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return (SIM_GpioPort(port)->ODR & pin) ? 1u : 0u;
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}
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static inline void LL_GPIO_SetPinMode(GPIO_TypeDef *port, uint32_t pin, uint32_t mode) { (void)port; (void)pin; (void)mode; }
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static inline void LL_GPIO_SetPinPull(GPIO_TypeDef *port, uint32_t pin, uint32_t pull) { (void)port; (void)pin; (void)pull; }
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static inline void LL_GPIO_SetPinOutputType(GPIO_TypeDef *port, uint32_t pin, uint32_t t) { (void)port; (void)pin; (void)t; }
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static inline void LL_GPIO_SetPinSpeed(GPIO_TypeDef *port, uint32_t pin, uint32_t s) { (void)port; (void)pin; (void)s; }
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#endif
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