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https://github.com/MCKero6423/uv-k5-v3-emulator.git
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mckero
c0a09827ed
Adds a QEMU machine for the Puya PY32F071 (Cortex-M0+) so Quansheng UV-K5 V3 firmware can run on a PC. The firmware boots to its main loop in about five seconds and the LCD contents are readable. Register layouts come from the vendor CMSIS header shipped with the firmware rather than guesswork. Modelled: RCC, GPIO, ADC, both SPI controllers, DMA1 and the PY25Q16 flash; everything else answers through a logging catch-all, which is how the next thing worth modelling gets identified. Seven things had to be right before it would boot, each found by watching where the firmware stopped: flash aliased at the application offset, clock ready bits, self-clearing ADC calibration, SPI transfer flags, DMA-driven flash reads, SysTick poll acceleration, and the bit-banged transceiver bus idling low. SysTick needs explanation. SYSTICK_DelayUs polls the counter and accumulates differences; under emulation a register read costs far more relative to guest time, so a measured 120 ms delay would have taken about 7.7 hours. Lowering the clock does not help because the bottleneck is loop iterations, not counter speed. Reporting a value that runs ahead of the real counter does, via a new poll-boost property on SysTick. Guest time therefore runs fast during delays: fine for exercising menus and control flow, wrong for judging signal timing. Also includes the host build of the CW timing chain (harness, stubs, shim, tests), which compiles app/cwkeyer.c and app/cwmacro.c unmodified against stub drivers with a virtual clock and scripted paddle input. Known gap: keypad rows reach the firmware's scan and KEYBOARD_Poll returns the right key code, but the UI does not react yet. Not modelled, and not intended to be: radio behaviour. The transceiver chip has no public datasheet, so keying envelopes and emissions need real hardware.
62 lines
1.5 KiB
Plaintext
62 lines
1.5 KiB
Plaintext
/*
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* ARMv7M SysTick timer
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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* Copyright (c) 2017 Linaro Ltd
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* Written by Peter Maydell
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*
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* This code is licensed under the GPL (version 2 or later).
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*/
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#ifndef HW_TIMER_ARMV7M_SYSTICK_H
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#define HW_TIMER_ARMV7M_SYSTICK_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "hw/ptimer.h"
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#include "hw/clock.h"
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#define TYPE_SYSTICK "armv7m_systick"
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OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
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/*
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* QEMU interface:
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* + sysbus MMIO region 0 is the register interface (covering
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* the registers which are mapped at address 0xE000E010)
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* + sysbus IRQ 0 is the interrupt line to the NVIC
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* + Clock input "refclk" is the external reference clock
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* (used when SYST_CSR.CLKSOURCE == 0)
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* + Clock input "cpuclk" is the main CPU clock
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* (used when SYST_CSR.CLKSOURCE == 1)
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*/
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struct SysTickState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t control;
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uint32_t reload;
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int64_t tick;
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ptimer_state *ptimer;
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MemoryRegion iomem;
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qemu_irq irq;
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Clock *refclk;
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Clock *cpuclk;
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/*
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* Ticks to additionally advance on each read of the current-value register,
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* so firmware busy-wait delay loops converge under emulation. Zero keeps
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* exact hardware behaviour and is the default; only boards that need it
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* set the "poll-boost" property.
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*/
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uint32_t poll_boost;
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/* Running total added by poll_boost, applied to reported counter values. */
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uint32_t poll_skew;
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};
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#endif
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