mirror of
https://github.com/MCKero6423/uv-k5-v3-emulator.git
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mckero
c0a09827ed
Adds a QEMU machine for the Puya PY32F071 (Cortex-M0+) so Quansheng UV-K5 V3 firmware can run on a PC. The firmware boots to its main loop in about five seconds and the LCD contents are readable. Register layouts come from the vendor CMSIS header shipped with the firmware rather than guesswork. Modelled: RCC, GPIO, ADC, both SPI controllers, DMA1 and the PY25Q16 flash; everything else answers through a logging catch-all, which is how the next thing worth modelling gets identified. Seven things had to be right before it would boot, each found by watching where the firmware stopped: flash aliased at the application offset, clock ready bits, self-clearing ADC calibration, SPI transfer flags, DMA-driven flash reads, SysTick poll acceleration, and the bit-banged transceiver bus idling low. SysTick needs explanation. SYSTICK_DelayUs polls the counter and accumulates differences; under emulation a register read costs far more relative to guest time, so a measured 120 ms delay would have taken about 7.7 hours. Lowering the clock does not help because the bottleneck is loop iterations, not counter speed. Reporting a value that runs ahead of the real counter does, via a new poll-boost property on SysTick. Guest time therefore runs fast during delays: fine for exercising menus and control flow, wrong for judging signal timing. Also includes the host build of the CW timing chain (harness, stubs, shim, tests), which compiles app/cwkeyer.c and app/cwmacro.c unmodified against stub drivers with a virtual clock and scripted paddle input. Known gap: keypad rows reach the firmware's scan and KEYBOARD_Poll returns the right key code, but the UI does not react yet. Not modelled, and not intended to be: radio behaviour. The transceiver chip has no public datasheet, so keying envelopes and emissions need real hardware.
84 lines
2.7 KiB
C
84 lines
2.7 KiB
C
/* The debounce and edge-detection half of app/cwhardware.c.
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*
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* Why this file exists: CW_ReadKeys() applies an asymmetric debounce (a press
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* needs three consecutive agreeing reads, a release takes effect on the first)
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* and tracks which paddle was pressed last for Ultimatic's tie-break. That logic
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* is part of the timing behaviour under test, so it must not be approximated.
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*
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* The rest of app/cwhardware.c is pin plumbing -- LL_GPIO_Init, DMA channels,
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* USB clock gating -- which needs 20+ MCU symbols and has no bearing on element
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* timing. Compiling the whole file would mean stubbing all of that.
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*
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* So the debounce is transcribed here, byte-for-byte in behaviour, and kept in
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* sync by a probe check (see check_sim_parity.py) that diffs it against the
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* firmware original. If someone edits the firmware debounce, the check fails.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "app/cwhardware.h"
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#include "settings.h"
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#define CW_KEY_FLAG_USB_PORT 0x20
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static bool s_last_dit;
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static bool s_last_dah;
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static bool s_last_is_dah;
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static uint8_t s_dit_count;
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static uint8_t s_dah_count;
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void CW_ReadKeys(CW_Input *in)
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{
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bool n_dit = false;
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bool n_dah = false;
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if (!CW_ReadKeysForMode(gEeprom.CW_KEY_INPUT, &n_dit, &n_dah)) {
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n_dit = false;
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n_dah = false;
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}
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bool deb_dit = s_last_dit;
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bool deb_dah = s_last_dah;
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if (gEeprom.CW_KEY_INPUT & CW_KEY_FLAG_USB_PORT) {
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// USB paddle has its own tri-state glitch filter upstream.
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deb_dit = n_dit;
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deb_dah = n_dah;
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} else {
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// Asymmetric: three-strike on rising, immediate on falling. A symmetric
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// release delay starves the iambic path's own count-based debounce and
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// makes mode B latch extra trailing elements.
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if (n_dit == deb_dit) s_dit_count = 0;
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else if (!deb_dit) {
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if (++s_dit_count >= 3) { deb_dit = true; s_dit_count = 0; }
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} else { deb_dit = false; s_dit_count = 0; }
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if (n_dah == deb_dah) s_dah_count = 0;
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else if (!deb_dah) {
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if (++s_dah_count >= 3) { deb_dah = true; s_dah_count = 0; }
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} else { deb_dah = false; s_dah_count = 0; }
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}
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in->dit_rise = (!s_last_dit && deb_dit);
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in->dah_rise = (!s_last_dah && deb_dah);
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in->dit = deb_dit;
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in->dah = deb_dah;
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// Most recent fresh press wins for Ultimatic's "both held" rule.
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if (in->dit_rise) s_last_is_dah = false;
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else if (in->dah_rise) s_last_is_dah = true;
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in->last_is_dah = s_last_is_dah;
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s_last_dit = deb_dit;
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s_last_dah = deb_dah;
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}
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void CW_HW_ResetKeySamples(void)
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{
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s_last_dit = false;
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s_last_dah = false;
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s_last_is_dah = false;
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s_dit_count = 0;
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s_dah_count = 0;
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}
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