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https://github.com/armel/uv-k1-k5v3-firmware-custom.git
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67 lines
2.7 KiB
C
67 lines
2.7 KiB
C
/* Copyright 2025 muzkr
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* https://github.com/muzkr
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef DRIVER_PY25Q16_H
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#define DRIVER_PY25Q16_H
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#include <stdint.h>
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#include <stdbool.h>
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void PY25Q16_Init();
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void PY25Q16_ReadBuffer(uint32_t Address, void *pBuffer, uint32_t Size);
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void PY25Q16_ReadBufferSafe(uint32_t Address, void *pBuffer, uint32_t Size);
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void PY25Q16_WriteBuffer(uint32_t Address, const void *pBuffer, uint32_t Size, bool Append);
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void PY25Q16_SectorErase(uint32_t Address);
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/* Drop the internal single-sector write cache. Call after erasing/programming
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* flash behind the driver's back (e.g. the raw multiboot slot/bank ops) so a
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* later write cannot skip or resurrect data based on a stale cached sector. It
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* is also called before multiboot reuses the cache storage as a RAM overlay. */
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void PY25Q16_InvalidateCache(void);
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#ifdef ENABLE_FEAT_F4HWN_OVERLAY_APPS
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/* The 4 KiB sector cache, reused as the overlay-app execution workspace. */
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uint8_t *PY25Q16_OverlayBuffer(void);
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#endif
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#ifdef ENABLE_FEAT_F4HWN_MULTIBOOT
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/*
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* Multiboot per-bank config banking.
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*
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* Each firmware slot gets its own config bank by default (memory channels,
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* names, VFOs, settings), though SetCfg can point the running firmware at a
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* different bank. A non-zero bank base transparently shifts every flash access
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* BELOW PY25Q16_BANK_SHARED_FROM into the active bank; calibration, boot logo,
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* firmware slots and the multiboot marker all live at/above that boundary and
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* stay shared across every bank.
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*
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* This is the single choke point: both the EEPROM emulation (eeprom_compat.c)
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* and the firmware's direct config reads/writes (settings.c) end up here, so
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* one offset covers them all - no per-call-site patching.
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*
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* Set once at boot, before any settings read, from
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* PY25Q16_SetBankBase(MB_BankBase(MB_BootResolveState()));
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* and never changed again during a session (a slot restore or SetCfg selection
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* records the next bank and resets first), so the banking itself never needs a
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* cache flush. Raw bank erases behind the driver explicitly call
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* PY25Q16_InvalidateCache().
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*/
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#define PY25Q16_BANK_SHARED_FROM 0x00010000u /* calibration boundary (see flash map) */
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void PY25Q16_SetBankBase(uint32_t Base);
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#endif
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#endif
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