mirror of
https://github.com/armel/uv-k1-k5v3-firmware-custom.git
synced 2026-10-02 03:15:37 +00:00
138 lines
4.1 KiB
C
138 lines
4.1 KiB
C
/* Copyright 2025 muzkr https://github.com/muzkr
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* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdbool.h>
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#include <string.h>
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#include "py32f071_ll_bus.h"
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#include "py32f071_ll_system.h"
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#include "py32f071_ll_dma.h"
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#include "py32f071_ll_gpio.h"
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#include "py32f071_ll_usart.h"
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#include "driver/uart.h"
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#define USARTx USART1
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#define DMA_CHANNEL LL_DMA_CHANNEL_2
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static bool UART_IsLogEnabled;
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uint8_t UART_DMA_Buffer[256];
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void UART_Init(void)
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{
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// PA9 TX
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// PA10 RX
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LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_USART1);
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// Pins
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do
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{
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LL_GPIO_InitTypeDef GPIO_InitStruct;
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LL_GPIO_StructInit(&GPIO_InitStruct);
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GPIO_InitStruct.Pin = LL_GPIO_PIN_9 | LL_GPIO_PIN_10;
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GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
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GPIO_InitStruct.Alternate = LL_GPIO_AF1_USART1;
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GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
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LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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} while (0);
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// DMA
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do
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{
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LL_DMA_DisableChannel(DMA1, DMA_CHANNEL);
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LL_DMA_InitTypeDef DMA_InitStruct;
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LL_DMA_StructInit(&DMA_InitStruct);
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DMA_InitStruct.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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DMA_InitStruct.Mode = LL_DMA_MODE_CIRCULAR;
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DMA_InitStruct.PeriphOrM2MSrcAddress = LL_USART_DMA_GetRegAddr(USARTx);
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DMA_InitStruct.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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DMA_InitStruct.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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DMA_InitStruct.MemoryOrM2MDstAddress = (uint32_t)UART_DMA_Buffer;
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DMA_InitStruct.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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DMA_InitStruct.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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DMA_InitStruct.NbData = sizeof(UART_DMA_Buffer);
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DMA_InitStruct.Priority = LL_DMA_PRIORITY_HIGH;
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LL_DMA_Init(DMA1, DMA_CHANNEL, &DMA_InitStruct);
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LL_SYSCFG_SetDMARemap(DMA1, DMA_CHANNEL, LL_SYSCFG_DMA_MAP_USART1_RD);
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} while (0);
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LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1);
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LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1);
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// USART
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do
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{
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LL_USART_Disable(USARTx);
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LL_USART_InitTypeDef USART_InitStruct;
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LL_USART_StructInit(&USART_InitStruct);
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USART_InitStruct.BaudRate = 38400;
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USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
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LL_USART_Init(USARTx, &USART_InitStruct);
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LL_USART_EnableDMAReq_RX(USARTx);
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} while (0);
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LL_DMA_EnableChannel(DMA1, DMA_CHANNEL);
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LL_USART_Enable(USARTx);
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LL_USART_TransmitData8(USARTx, 0);
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}
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void UART_Send(const void *pBuffer, uint32_t Size)
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{
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const uint8_t *pData = (const uint8_t *)pBuffer;
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uint32_t i;
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for (i = 0; i < Size; i++)
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{
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while (!LL_USART_IsActiveFlag_TXE(USARTx))
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;
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LL_USART_TransmitData8(USARTx, pData[i]);
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}
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}
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void UART_LogSend(const void *pBuffer, uint32_t Size)
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{
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if (UART_IsLogEnabled) {
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UART_Send(pBuffer, Size);
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}
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}
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#ifdef ENABLE_FEAT_F4HWN_SCREENSHOT
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bool UART_IsCableConnected(void) {
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for (size_t i = 0; i < sizeof(UART_DMA_Buffer); i++) {
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if (UART_DMA_Buffer[i] == 0x55) {
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UART_DMA_Buffer[i] = 0x00; // Clear only the matched byte
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return true;
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}
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}
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return false;
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}
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#endif
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