From fa52b8d0ad6204b47a4c823341a0b251d43ccd6d Mon Sep 17 00:00:00 2001 From: muzkr <> Date: Thu, 27 Nov 2025 06:15:41 +0800 Subject: [PATCH] Delete legacy DP32G030 artefacrs --- App/bsp/dp32g030/aes.h | 87 -- App/bsp/dp32g030/crc.h | 109 -- App/bsp/dp32g030/dma.h | 319 ------ App/bsp/dp32g030/flash.h | 165 --- App/bsp/dp32g030/gpio.h | 176 --- App/bsp/dp32g030/irq.h | 40 - App/bsp/dp32g030/pmu.h | 65 -- App/bsp/dp32g030/portcon.h | 2174 ------------------------------------ App/bsp/dp32g030/pwmplus.h | 146 --- App/bsp/dp32g030/saradc.h | 253 ----- App/bsp/dp32g030/spi.h | 240 ---- App/bsp/dp32g030/syscon.h | 348 ------ App/bsp/dp32g030/uart.h | 439 -------- App/driver/flash.h | 26 +- App/firmware.ld | 79 -- App/start.S | 253 ----- 16 files changed, 12 insertions(+), 4907 deletions(-) delete mode 100644 App/bsp/dp32g030/aes.h delete mode 100644 App/bsp/dp32g030/crc.h delete mode 100644 App/bsp/dp32g030/dma.h delete mode 100644 App/bsp/dp32g030/flash.h delete mode 100644 App/bsp/dp32g030/gpio.h delete mode 100644 App/bsp/dp32g030/irq.h delete mode 100644 App/bsp/dp32g030/pmu.h delete mode 100644 App/bsp/dp32g030/portcon.h delete mode 100644 App/bsp/dp32g030/pwmplus.h delete mode 100644 App/bsp/dp32g030/saradc.h delete mode 100644 App/bsp/dp32g030/spi.h delete mode 100644 App/bsp/dp32g030/syscon.h delete mode 100644 App/bsp/dp32g030/uart.h delete mode 100644 App/firmware.ld delete mode 100644 App/start.S diff --git a/App/bsp/dp32g030/aes.h b/App/bsp/dp32g030/aes.h deleted file mode 100644 index c5cc39fb..00000000 --- a/App/bsp/dp32g030/aes.h +++ /dev/null @@ -1,87 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_AES_H -#define HARDWARE_DP32G030_AES_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- AES -------- */ -#define AES_BASE_ADDR 0x400BD000U -#define AES_BASE_SIZE 0x00000800U - -#define AES_CR_ADDR (AES_BASE_ADDR + 0x0000U) -#define AES_CR (*(volatile uint32_t *)AES_CR_ADDR) -#define AES_CR_EN_SHIFT 0 -#define AES_CR_EN_WIDTH 1 -#define AES_CR_EN_MASK (((1U << AES_CR_EN_WIDTH) - 1U) << AES_CR_EN_SHIFT) -#define AES_CR_EN_VALUE_DISABLE 0U -#define AES_CR_EN_BITS_DISABLE (AES_CR_EN_VALUE_DISABLE << AES_CR_EN_SHIFT) -#define AES_CR_EN_VALUE_ENABLE 1U -#define AES_CR_EN_BITS_ENABLE (AES_CR_EN_VALUE_ENABLE << AES_CR_EN_SHIFT) - -#define AES_CR_CHMOD_SHIFT 5 -#define AES_CR_CHMOD_WIDTH 2 -#define AES_CR_CHMOD_MASK (((1U << AES_CR_CHMOD_WIDTH) - 1U) << AES_CR_CHMOD_SHIFT) -#define AES_CR_CHMOD_VALUE_ECB 0U -#define AES_CR_CHMOD_BITS_ECB (AES_CR_CHMOD_VALUE_ECB << AES_CR_CHMOD_SHIFT) -#define AES_CR_CHMOD_VALUE_CBC 1U -#define AES_CR_CHMOD_BITS_CBC (AES_CR_CHMOD_VALUE_CBC << AES_CR_CHMOD_SHIFT) -#define AES_CR_CHMOD_VALUE_CTR 2U -#define AES_CR_CHMOD_BITS_CTR (AES_CR_CHMOD_VALUE_CTR << AES_CR_CHMOD_SHIFT) - -#define AES_CR_CCFC_SHIFT 7 -#define AES_CR_CCFC_WIDTH 1 -#define AES_CR_CCFC_MASK (((1U << AES_CR_CCFC_WIDTH) - 1U) << AES_CR_CCFC_SHIFT) -#define AES_CR_CCFC_VALUE_SET 1U -#define AES_CR_CCFC_BITS_SET (AES_CR_CCFC_VALUE_SET << AES_CR_CCFC_SHIFT) - -#define AES_SR_ADDR (AES_BASE_ADDR + 0x0004U) -#define AES_SR (*(volatile uint32_t *)AES_SR_ADDR) -#define AES_SR_CCF_SHIFT 0 -#define AES_SR_CCF_WIDTH 1 -#define AES_SR_CCF_MASK (((1U << AES_SR_CCF_WIDTH) - 1U) << AES_SR_CCF_SHIFT) -#define AES_SR_CCF_VALUE_NOT_COMPLETE 0U -#define AES_SR_CCF_BITS_NOT_COMPLETE (AES_SR_CCF_VALUE_NOT_COMPLETE << AES_SR_CCF_SHIFT) -#define AES_SR_CCF_VALUE_COMPLETE 1U -#define AES_SR_CCF_BITS_COMPLETE (AES_SR_CCF_VALUE_COMPLETE << AES_SR_CCF_SHIFT) - -#define AES_DINR_ADDR (AES_BASE_ADDR + 0x0008U) -#define AES_DINR (*(volatile uint32_t *)AES_DINR_ADDR) -#define AES_DOUTR_ADDR (AES_BASE_ADDR + 0x000CU) -#define AES_DOUTR (*(volatile uint32_t *)AES_DOUTR_ADDR) -#define AES_KEYR0_ADDR (AES_BASE_ADDR + 0x0010U) -#define AES_KEYR0 (*(volatile uint32_t *)AES_KEYR0_ADDR) -#define AES_KEYR1_ADDR (AES_BASE_ADDR + 0x0014U) -#define AES_KEYR1 (*(volatile uint32_t *)AES_KEYR1_ADDR) -#define AES_KEYR2_ADDR (AES_BASE_ADDR + 0x0018U) -#define AES_KEYR2 (*(volatile uint32_t *)AES_KEYR2_ADDR) -#define AES_KEYR3_ADDR (AES_BASE_ADDR + 0x001CU) -#define AES_KEYR3 (*(volatile uint32_t *)AES_KEYR3_ADDR) -#define AES_IVR0_ADDR (AES_BASE_ADDR + 0x0020U) -#define AES_IVR0 (*(volatile uint32_t *)AES_IVR0_ADDR) -#define AES_IVR1_ADDR (AES_BASE_ADDR + 0x0024U) -#define AES_IVR1 (*(volatile uint32_t *)AES_IVR1_ADDR) -#define AES_IVR2_ADDR (AES_BASE_ADDR + 0x0028U) -#define AES_IVR2 (*(volatile uint32_t *)AES_IVR2_ADDR) -#define AES_IVR3_ADDR (AES_BASE_ADDR + 0x002CU) -#define AES_IVR3 (*(volatile uint32_t *)AES_IVR3_ADDR) - - -#endif - diff --git a/App/bsp/dp32g030/crc.h b/App/bsp/dp32g030/crc.h deleted file mode 100644 index 83c9a7a3..00000000 --- a/App/bsp/dp32g030/crc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_CRC_H -#define HARDWARE_DP32G030_CRC_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- CRC -------- */ -#define CRC_BASE_ADDR 0x40003000U -#define CRC_BASE_SIZE 0x00000800U - -#define CRC_CR_ADDR (CRC_BASE_ADDR + 0x0000U) -#define CRC_CR (*(volatile uint32_t *)CRC_CR_ADDR) -#define CRC_CR_CRC_EN_SHIFT 0 -#define CRC_CR_CRC_EN_WIDTH 1 -#define CRC_CR_CRC_EN_MASK (((1U << CRC_CR_CRC_EN_WIDTH) - 1U) << CRC_CR_CRC_EN_SHIFT) -#define CRC_CR_CRC_EN_VALUE_DISABLE 0U -#define CRC_CR_CRC_EN_BITS_DISABLE (CRC_CR_CRC_EN_VALUE_DISABLE << CRC_CR_CRC_EN_SHIFT) -#define CRC_CR_CRC_EN_VALUE_ENABLE 1U -#define CRC_CR_CRC_EN_BITS_ENABLE (CRC_CR_CRC_EN_VALUE_ENABLE << CRC_CR_CRC_EN_SHIFT) - -#define CRC_CR_INPUT_REV_SHIFT 1 -#define CRC_CR_INPUT_REV_WIDTH 1 -#define CRC_CR_INPUT_REV_MASK (((1U << CRC_CR_INPUT_REV_WIDTH) - 1U) << CRC_CR_INPUT_REV_SHIFT) -#define CRC_CR_INPUT_REV_VALUE_NORMAL 0U -#define CRC_CR_INPUT_REV_BITS_NORMAL (CRC_CR_INPUT_REV_VALUE_NORMAL << CRC_CR_INPUT_REV_SHIFT) -#define CRC_CR_INPUT_REV_VALUE_REVERSED 1U -#define CRC_CR_INPUT_REV_BITS_REVERSED (CRC_CR_INPUT_REV_VALUE_REVERSED << CRC_CR_INPUT_REV_SHIFT) - -#define CRC_CR_INPUT_INV_SHIFT 2 -#define CRC_CR_INPUT_INV_WIDTH 2 -#define CRC_CR_INPUT_INV_MASK (((1U << CRC_CR_INPUT_INV_WIDTH) - 1U) << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_VALUE_NORMAL 0U -#define CRC_CR_INPUT_INV_BITS_NORMAL (CRC_CR_INPUT_INV_VALUE_NORMAL << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_VALUE_BIT_INVERTED 1U -#define CRC_CR_INPUT_INV_BITS_BIT_INVERTED (CRC_CR_INPUT_INV_VALUE_BIT_INVERTED << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED 2U -#define CRC_CR_INPUT_INV_BITS_BYTE_INVERTED (CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT) -#define CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED 3U -#define CRC_CR_INPUT_INV_BITS_BIT_BYTE_INVERTED (CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT) - -#define CRC_CR_OUTPUT_REV_SHIFT 4 -#define CRC_CR_OUTPUT_REV_WIDTH 1 -#define CRC_CR_OUTPUT_REV_MASK (((1U << CRC_CR_OUTPUT_REV_WIDTH) - 1U) << CRC_CR_OUTPUT_REV_SHIFT) -#define CRC_CR_OUTPUT_REV_VALUE_NORMAL 0U -#define CRC_CR_OUTPUT_REV_BITS_NORMAL (CRC_CR_OUTPUT_REV_VALUE_NORMAL << CRC_CR_OUTPUT_REV_SHIFT) -#define CRC_CR_OUTPUT_REV_VALUE_REVERSED 1U -#define CRC_CR_OUTPUT_REV_BITS_REVERSED (CRC_CR_OUTPUT_REV_VALUE_REVERSED << CRC_CR_OUTPUT_REV_SHIFT) - -#define CRC_CR_OUTPUT_INV_SHIFT 5 -#define CRC_CR_OUTPUT_INV_WIDTH 2 -#define CRC_CR_OUTPUT_INV_MASK (((1U << CRC_CR_OUTPUT_INV_WIDTH) - 1U) << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_VALUE_NORMAL 0U -#define CRC_CR_OUTPUT_INV_BITS_NORMAL (CRC_CR_OUTPUT_INV_VALUE_NORMAL << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED 1U -#define CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED 2U -#define CRC_CR_OUTPUT_INV_BITS_BYTE_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) -#define CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED 3U -#define CRC_CR_OUTPUT_INV_BITS_BIT_BYTE_INVERTED (CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT) - -#define CRC_CR_DATA_WIDTH_SHIFT 7 -#define CRC_CR_DATA_WIDTH_WIDTH 2 -#define CRC_CR_DATA_WIDTH_MASK (((1U << CRC_CR_DATA_WIDTH_WIDTH) - 1U) << CRC_CR_DATA_WIDTH_SHIFT) -#define CRC_CR_DATA_WIDTH_VALUE_32 0U -#define CRC_CR_DATA_WIDTH_BITS_32 (CRC_CR_DATA_WIDTH_VALUE_32 << CRC_CR_DATA_WIDTH_SHIFT) -#define CRC_CR_DATA_WIDTH_VALUE_16 1U -#define CRC_CR_DATA_WIDTH_BITS_16 (CRC_CR_DATA_WIDTH_VALUE_16 << CRC_CR_DATA_WIDTH_SHIFT) -#define CRC_CR_DATA_WIDTH_VALUE_8 2U -#define CRC_CR_DATA_WIDTH_BITS_8 (CRC_CR_DATA_WIDTH_VALUE_8 << CRC_CR_DATA_WIDTH_SHIFT) - -#define CRC_CR_CRC_SEL_SHIFT 9 -#define CRC_CR_CRC_SEL_WIDTH 2 -#define CRC_CR_CRC_SEL_MASK (((1U << CRC_CR_CRC_SEL_WIDTH) - 1U) << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT 0U -#define CRC_CR_CRC_SEL_BITS_CRC_16_CCITT (CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_VALUE_CRC_8_ATM 1U -#define CRC_CR_CRC_SEL_BITS_CRC_8_ATM (CRC_CR_CRC_SEL_VALUE_CRC_8_ATM << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_VALUE_CRC_16 2U -#define CRC_CR_CRC_SEL_BITS_CRC_16 (CRC_CR_CRC_SEL_VALUE_CRC_16 << CRC_CR_CRC_SEL_SHIFT) -#define CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3 3U -#define CRC_CR_CRC_SEL_BITS_CRC_32_IEEE802_3 (CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3 << CRC_CR_CRC_SEL_SHIFT) - -#define CRC_IV_ADDR (CRC_BASE_ADDR + 0x0004U) -#define CRC_IV (*(volatile uint32_t *)CRC_IV_ADDR) -#define CRC_DATAIN_ADDR (CRC_BASE_ADDR + 0x0008U) -#define CRC_DATAIN (*(volatile uint32_t *)CRC_DATAIN_ADDR) -#define CRC_DATAOUT_ADDR (CRC_BASE_ADDR + 0x000CU) -#define CRC_DATAOUT (*(volatile uint32_t *)CRC_DATAOUT_ADDR) - - -#endif - diff --git a/App/bsp/dp32g030/dma.h b/App/bsp/dp32g030/dma.h deleted file mode 100644 index 4ec67b62..00000000 --- a/App/bsp/dp32g030/dma.h +++ /dev/null @@ -1,319 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_DMA_H -#define HARDWARE_DP32G030_DMA_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- DMA -------- */ -#define DMA_BASE_ADDR 0x40001000U -#define DMA_BASE_SIZE 0x00000100U - -#define DMA_CTR_ADDR (DMA_BASE_ADDR + 0x0000U) -#define DMA_CTR (*(volatile uint32_t *)DMA_CTR_ADDR) -#define DMA_CTR_DMAEN_SHIFT 0 -#define DMA_CTR_DMAEN_WIDTH 1 -#define DMA_CTR_DMAEN_MASK (((1U << DMA_CTR_DMAEN_WIDTH) - 1U) << DMA_CTR_DMAEN_SHIFT) -#define DMA_CTR_DMAEN_VALUE_DISABLE 0U -#define DMA_CTR_DMAEN_BITS_DISABLE (DMA_CTR_DMAEN_VALUE_DISABLE << DMA_CTR_DMAEN_SHIFT) -#define DMA_CTR_DMAEN_VALUE_ENABLE 1U -#define DMA_CTR_DMAEN_BITS_ENABLE (DMA_CTR_DMAEN_VALUE_ENABLE << DMA_CTR_DMAEN_SHIFT) - -#define DMA_INTEN_ADDR (DMA_BASE_ADDR + 0x0004U) -#define DMA_INTEN (*(volatile uint32_t *)DMA_INTEN_ADDR) -#define DMA_INTEN_CH0_TC_INTEN_SHIFT 0 -#define DMA_INTEN_CH0_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH0_TC_INTEN_MASK (((1U << DMA_INTEN_CH0_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_TC_INTEN_SHIFT) -#define DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH0_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT) -#define DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH0_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT) - -#define DMA_INTEN_CH1_TC_INTEN_SHIFT 1 -#define DMA_INTEN_CH1_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH1_TC_INTEN_MASK (((1U << DMA_INTEN_CH1_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_TC_INTEN_SHIFT) -#define DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH1_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT) -#define DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH1_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT) - -#define DMA_INTEN_CH2_TC_INTEN_SHIFT 2 -#define DMA_INTEN_CH2_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH2_TC_INTEN_MASK (((1U << DMA_INTEN_CH2_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_TC_INTEN_SHIFT) -#define DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH2_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT) -#define DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH2_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT) - -#define DMA_INTEN_CH3_TC_INTEN_SHIFT 3 -#define DMA_INTEN_CH3_TC_INTEN_WIDTH 1 -#define DMA_INTEN_CH3_TC_INTEN_MASK (((1U << DMA_INTEN_CH3_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_TC_INTEN_SHIFT) -#define DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH3_TC_INTEN_BITS_DISABLE (DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT) -#define DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH3_TC_INTEN_BITS_ENABLE (DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT) - -#define DMA_INTEN_CH0_THC_INTEN_SHIFT 8 -#define DMA_INTEN_CH0_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH0_THC_INTEN_MASK (((1U << DMA_INTEN_CH0_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_THC_INTEN_SHIFT) -#define DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH0_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT) -#define DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH0_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT) - -#define DMA_INTEN_CH1_THC_INTEN_SHIFT 9 -#define DMA_INTEN_CH1_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH1_THC_INTEN_MASK (((1U << DMA_INTEN_CH1_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_THC_INTEN_SHIFT) -#define DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH1_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT) -#define DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH1_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT) - -#define DMA_INTEN_CH2_THC_INTEN_SHIFT 10 -#define DMA_INTEN_CH2_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH2_THC_INTEN_MASK (((1U << DMA_INTEN_CH2_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_THC_INTEN_SHIFT) -#define DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH2_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT) -#define DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH2_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT) - -#define DMA_INTEN_CH3_THC_INTEN_SHIFT 11 -#define DMA_INTEN_CH3_THC_INTEN_WIDTH 1 -#define DMA_INTEN_CH3_THC_INTEN_MASK (((1U << DMA_INTEN_CH3_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_THC_INTEN_SHIFT) -#define DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE 0U -#define DMA_INTEN_CH3_THC_INTEN_BITS_DISABLE (DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT) -#define DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE 1U -#define DMA_INTEN_CH3_THC_INTEN_BITS_ENABLE (DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT) - -#define DMA_INTST_ADDR (DMA_BASE_ADDR + 0x0008U) -#define DMA_INTST (*(volatile uint32_t *)DMA_INTST_ADDR) -#define DMA_INTST_CH0_TC_INTST_SHIFT 0 -#define DMA_INTST_CH0_TC_INTST_WIDTH 1 -#define DMA_INTST_CH0_TC_INTST_MASK (((1U << DMA_INTST_CH0_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_TC_INTST_SHIFT) -#define DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH0_TC_INTST_BITS_NOT_SET (DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_TC_INTST_SHIFT) -#define DMA_INTST_CH0_TC_INTST_VALUE_SET 1U -#define DMA_INTST_CH0_TC_INTST_BITS_SET (DMA_INTST_CH0_TC_INTST_VALUE_SET << DMA_INTST_CH0_TC_INTST_SHIFT) - -#define DMA_INTST_CH1_TC_INTST_SHIFT 1 -#define DMA_INTST_CH1_TC_INTST_WIDTH 1 -#define DMA_INTST_CH1_TC_INTST_MASK (((1U << DMA_INTST_CH1_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_TC_INTST_SHIFT) -#define DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH1_TC_INTST_BITS_NOT_SET (DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_TC_INTST_SHIFT) -#define DMA_INTST_CH1_TC_INTST_VALUE_SET 1U -#define DMA_INTST_CH1_TC_INTST_BITS_SET (DMA_INTST_CH1_TC_INTST_VALUE_SET << DMA_INTST_CH1_TC_INTST_SHIFT) - -#define DMA_INTST_CH2_TC_INTST_SHIFT 2 -#define DMA_INTST_CH2_TC_INTST_WIDTH 1 -#define DMA_INTST_CH2_TC_INTST_MASK (((1U << DMA_INTST_CH2_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_TC_INTST_SHIFT) -#define DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH2_TC_INTST_BITS_NOT_SET (DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_TC_INTST_SHIFT) -#define DMA_INTST_CH2_TC_INTST_VALUE_SET 1U -#define DMA_INTST_CH2_TC_INTST_BITS_SET (DMA_INTST_CH2_TC_INTST_VALUE_SET << DMA_INTST_CH2_TC_INTST_SHIFT) - -#define DMA_INTST_CH3_TC_INTST_SHIFT 3 -#define DMA_INTST_CH3_TC_INTST_WIDTH 1 -#define DMA_INTST_CH3_TC_INTST_MASK (((1U << DMA_INTST_CH3_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_TC_INTST_SHIFT) -#define DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH3_TC_INTST_BITS_NOT_SET (DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_TC_INTST_SHIFT) -#define DMA_INTST_CH3_TC_INTST_VALUE_SET 1U -#define DMA_INTST_CH3_TC_INTST_BITS_SET (DMA_INTST_CH3_TC_INTST_VALUE_SET << DMA_INTST_CH3_TC_INTST_SHIFT) - -#define DMA_INTST_CH0_THC_INTST_SHIFT 8 -#define DMA_INTST_CH0_THC_INTST_WIDTH 1 -#define DMA_INTST_CH0_THC_INTST_MASK (((1U << DMA_INTST_CH0_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_THC_INTST_SHIFT) -#define DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH0_THC_INTST_BITS_NOT_SET (DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_THC_INTST_SHIFT) -#define DMA_INTST_CH0_THC_INTST_VALUE_SET 1U -#define DMA_INTST_CH0_THC_INTST_BITS_SET (DMA_INTST_CH0_THC_INTST_VALUE_SET << DMA_INTST_CH0_THC_INTST_SHIFT) - -#define DMA_INTST_CH1_THC_INTST_SHIFT 9 -#define DMA_INTST_CH1_THC_INTST_WIDTH 1 -#define DMA_INTST_CH1_THC_INTST_MASK (((1U << DMA_INTST_CH1_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_THC_INTST_SHIFT) -#define DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH1_THC_INTST_BITS_NOT_SET (DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_THC_INTST_SHIFT) -#define DMA_INTST_CH1_THC_INTST_VALUE_SET 1U -#define DMA_INTST_CH1_THC_INTST_BITS_SET (DMA_INTST_CH1_THC_INTST_VALUE_SET << DMA_INTST_CH1_THC_INTST_SHIFT) - -#define DMA_INTST_CH2_THC_INTST_SHIFT 10 -#define DMA_INTST_CH2_THC_INTST_WIDTH 1 -#define DMA_INTST_CH2_THC_INTST_MASK (((1U << DMA_INTST_CH2_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_THC_INTST_SHIFT) -#define DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH2_THC_INTST_BITS_NOT_SET (DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_THC_INTST_SHIFT) -#define DMA_INTST_CH2_THC_INTST_VALUE_SET 1U -#define DMA_INTST_CH2_THC_INTST_BITS_SET (DMA_INTST_CH2_THC_INTST_VALUE_SET << DMA_INTST_CH2_THC_INTST_SHIFT) - -#define DMA_INTST_CH3_THC_INTST_SHIFT 11 -#define DMA_INTST_CH3_THC_INTST_WIDTH 1 -#define DMA_INTST_CH3_THC_INTST_MASK (((1U << DMA_INTST_CH3_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_THC_INTST_SHIFT) -#define DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET 0U -#define DMA_INTST_CH3_THC_INTST_BITS_NOT_SET (DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_THC_INTST_SHIFT) -#define DMA_INTST_CH3_THC_INTST_VALUE_SET 1U -#define DMA_INTST_CH3_THC_INTST_BITS_SET (DMA_INTST_CH3_THC_INTST_VALUE_SET << DMA_INTST_CH3_THC_INTST_SHIFT) - -/* -------- DMA_CH0 -------- */ -#define DMA_CH0_BASE_ADDR 0x40001100U -#define DMA_CH0_BASE_SIZE 0x00000020U -#define DMA_CH0 ((volatile DMA_Channel_t *)DMA_CH0_BASE_ADDR) - -/* -------- DMA_CH1 -------- */ -#define DMA_CH1_BASE_ADDR 0x40001120U -#define DMA_CH1_BASE_SIZE 0x00000020U -#define DMA_CH1 ((volatile DMA_Channel_t *)DMA_CH1_BASE_ADDR) - -/* -------- DMA_CH2 -------- */ -#define DMA_CH2_BASE_ADDR 0x40001140U -#define DMA_CH2_BASE_SIZE 0x00000020U -#define DMA_CH2 ((volatile DMA_Channel_t *)DMA_CH2_BASE_ADDR) - -/* -------- DMA_CH3 -------- */ -#define DMA_CH3_BASE_ADDR 0x40001160U -#define DMA_CH3_BASE_SIZE 0x00000020U -#define DMA_CH3 ((volatile DMA_Channel_t *)DMA_CH3_BASE_ADDR) - -/* -------- DMA_CH -------- */ - -typedef struct { - uint32_t CTR; - uint32_t MOD; - uint32_t MSADDR; - uint32_t MDADDR; - uint32_t ST; -} DMA_Channel_t; - -#define DMA_CH_CTR_CH_EN_SHIFT 0 -#define DMA_CH_CTR_CH_EN_WIDTH 1 -#define DMA_CH_CTR_CH_EN_MASK (((1U << DMA_CH_CTR_CH_EN_WIDTH) - 1U) << DMA_CH_CTR_CH_EN_SHIFT) -#define DMA_CH_CTR_CH_EN_VALUE_DISABLE 0U -#define DMA_CH_CTR_CH_EN_BITS_DISABLE (DMA_CH_CTR_CH_EN_VALUE_DISABLE << DMA_CH_CTR_CH_EN_SHIFT) -#define DMA_CH_CTR_CH_EN_VALUE_ENABLE 1U -#define DMA_CH_CTR_CH_EN_BITS_ENABLE (DMA_CH_CTR_CH_EN_VALUE_ENABLE << DMA_CH_CTR_CH_EN_SHIFT) - -#define DMA_CH_CTR_LENGTH_SHIFT 1 -#define DMA_CH_CTR_LENGTH_WIDTH 12 -#define DMA_CH_CTR_LENGTH_MASK (((1U << DMA_CH_CTR_LENGTH_WIDTH) - 1U) << DMA_CH_CTR_LENGTH_SHIFT) -#define DMA_CH_CTR_LOOP_SHIFT 13 -#define DMA_CH_CTR_LOOP_WIDTH 1 -#define DMA_CH_CTR_LOOP_MASK (((1U << DMA_CH_CTR_LOOP_WIDTH) - 1U) << DMA_CH_CTR_LOOP_SHIFT) -#define DMA_CH_CTR_LOOP_VALUE_DISABLE 0U -#define DMA_CH_CTR_LOOP_BITS_DISABLE (DMA_CH_CTR_LOOP_VALUE_DISABLE << DMA_CH_CTR_LOOP_SHIFT) -#define DMA_CH_CTR_LOOP_VALUE_ENABLE 1U -#define DMA_CH_CTR_LOOP_BITS_ENABLE (DMA_CH_CTR_LOOP_VALUE_ENABLE << DMA_CH_CTR_LOOP_SHIFT) - -#define DMA_CH_CTR_PRI_SHIFT 14 -#define DMA_CH_CTR_PRI_WIDTH 2 -#define DMA_CH_CTR_PRI_MASK (((1U << DMA_CH_CTR_PRI_WIDTH) - 1U) << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_VALUE_LOW 0U -#define DMA_CH_CTR_PRI_BITS_LOW (DMA_CH_CTR_PRI_VALUE_LOW << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_VALUE_MEDIUM 1U -#define DMA_CH_CTR_PRI_BITS_MEDIUM (DMA_CH_CTR_PRI_VALUE_MEDIUM << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_VALUE_HIGH 2U -#define DMA_CH_CTR_PRI_BITS_HIGH (DMA_CH_CTR_PRI_VALUE_HIGH << DMA_CH_CTR_PRI_SHIFT) -#define DMA_CH_CTR_PRI_VALUE_HIGHEST 3U -#define DMA_CH_CTR_PRI_BITS_HIGHEST (DMA_CH_CTR_PRI_VALUE_HIGHEST << DMA_CH_CTR_PRI_SHIFT) - -#define DMA_CH_CTR_SWREQ_SHIFT 16 -#define DMA_CH_CTR_SWREQ_WIDTH 1 -#define DMA_CH_CTR_SWREQ_MASK (((1U << DMA_CH_CTR_SWREQ_WIDTH) - 1U) << DMA_CH_CTR_SWREQ_SHIFT) -#define DMA_CH_CTR_SWREQ_VALUE_SET 1U -#define DMA_CH_CTR_SWREQ_BITS_SET (DMA_CH_CTR_SWREQ_VALUE_SET << DMA_CH_CTR_SWREQ_SHIFT) - -#define DMA_CH_MOD_MS_ADDMOD_SHIFT 0 -#define DMA_CH_MOD_MS_ADDMOD_WIDTH 1 -#define DMA_CH_MOD_MS_ADDMOD_MASK (((1U << DMA_CH_MOD_MS_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MS_ADDMOD_SHIFT) -#define DMA_CH_MOD_MS_ADDMOD_VALUE_NONE 0U -#define DMA_CH_MOD_MS_ADDMOD_BITS_NONE (DMA_CH_MOD_MS_ADDMOD_VALUE_NONE << DMA_CH_MOD_MS_ADDMOD_SHIFT) -#define DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT 1U -#define DMA_CH_MOD_MS_ADDMOD_BITS_INCREMENT (DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MS_ADDMOD_SHIFT) - -#define DMA_CH_MOD_MS_SIZE_SHIFT 1 -#define DMA_CH_MOD_MS_SIZE_WIDTH 2 -#define DMA_CH_MOD_MS_SIZE_MASK (((1U << DMA_CH_MOD_MS_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_VALUE_8BIT 0U -#define DMA_CH_MOD_MS_SIZE_BITS_8BIT (DMA_CH_MOD_MS_SIZE_VALUE_8BIT << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_VALUE_16BIT 1U -#define DMA_CH_MOD_MS_SIZE_BITS_16BIT (DMA_CH_MOD_MS_SIZE_VALUE_16BIT << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_VALUE_32BIT 2U -#define DMA_CH_MOD_MS_SIZE_BITS_32BIT (DMA_CH_MOD_MS_SIZE_VALUE_32BIT << DMA_CH_MOD_MS_SIZE_SHIFT) -#define DMA_CH_MOD_MS_SIZE_VALUE_KEEP 3U -#define DMA_CH_MOD_MS_SIZE_BITS_KEEP (DMA_CH_MOD_MS_SIZE_VALUE_KEEP << DMA_CH_MOD_MS_SIZE_SHIFT) - -#define DMA_CH_MOD_MS_SEL_SHIFT 3 -#define DMA_CH_MOD_MS_SEL_WIDTH 3 -#define DMA_CH_MOD_MS_SEL_MASK (((1U << DMA_CH_MOD_MS_SEL_WIDTH) - 1U) << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_SRAM 0U -#define DMA_CH_MOD_MS_SEL_BITS_SRAM (DMA_CH_MOD_MS_SEL_VALUE_SRAM << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0 1U -#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS0 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1 2U -#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2 3U -#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS2 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3 4U -#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS3 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4 5U -#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS4 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5 6U -#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS5 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MS_SEL_SHIFT) -#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6 7U -#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS6 (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MS_SEL_SHIFT) - -#define DMA_CH_MOD_MD_ADDMOD_SHIFT 8 -#define DMA_CH_MOD_MD_ADDMOD_WIDTH 1 -#define DMA_CH_MOD_MD_ADDMOD_MASK (((1U << DMA_CH_MOD_MD_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MD_ADDMOD_SHIFT) -#define DMA_CH_MOD_MD_ADDMOD_VALUE_NONE 0U -#define DMA_CH_MOD_MD_ADDMOD_BITS_NONE (DMA_CH_MOD_MD_ADDMOD_VALUE_NONE << DMA_CH_MOD_MD_ADDMOD_SHIFT) -#define DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT 1U -#define DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT (DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MD_ADDMOD_SHIFT) - -#define DMA_CH_MOD_MD_SIZE_SHIFT 9 -#define DMA_CH_MOD_MD_SIZE_WIDTH 2 -#define DMA_CH_MOD_MD_SIZE_MASK (((1U << DMA_CH_MOD_MD_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_VALUE_8BIT 0U -#define DMA_CH_MOD_MD_SIZE_BITS_8BIT (DMA_CH_MOD_MD_SIZE_VALUE_8BIT << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_VALUE_16BIT 1U -#define DMA_CH_MOD_MD_SIZE_BITS_16BIT (DMA_CH_MOD_MD_SIZE_VALUE_16BIT << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_VALUE_32BIT 2U -#define DMA_CH_MOD_MD_SIZE_BITS_32BIT (DMA_CH_MOD_MD_SIZE_VALUE_32BIT << DMA_CH_MOD_MD_SIZE_SHIFT) -#define DMA_CH_MOD_MD_SIZE_VALUE_KEEP 3U -#define DMA_CH_MOD_MD_SIZE_BITS_KEEP (DMA_CH_MOD_MD_SIZE_VALUE_KEEP << DMA_CH_MOD_MD_SIZE_SHIFT) - -#define DMA_CH_MOD_MD_SEL_SHIFT 11 -#define DMA_CH_MOD_MD_SEL_WIDTH 3 -#define DMA_CH_MOD_MD_SEL_MASK (((1U << DMA_CH_MOD_MD_SEL_WIDTH) - 1U) << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_SRAM 0U -#define DMA_CH_MOD_MD_SEL_BITS_SRAM (DMA_CH_MOD_MD_SEL_VALUE_SRAM << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0 1U -#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS0 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1 2U -#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS1 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2 3U -#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS2 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3 4U -#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS3 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4 5U -#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS4 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5 6U -#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS5 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MD_SEL_SHIFT) -#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6 7U -#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS6 (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MD_SEL_SHIFT) - - -#endif - diff --git a/App/bsp/dp32g030/flash.h b/App/bsp/dp32g030/flash.h deleted file mode 100644 index f17b3d0f..00000000 --- a/App/bsp/dp32g030/flash.h +++ /dev/null @@ -1,165 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_FLASH_H -#define HARDWARE_DP32G030_FLASH_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- FLASH -------- */ -#define FLASH_BASE_ADDR 0x4006F000U -#define FLASH_BASE_SIZE 0x00000800U - -#define FLASH_CFG_ADDR (FLASH_BASE_ADDR + 0x0000U) -#define FLASH_CFG (*(volatile uint32_t *)FLASH_CFG_ADDR) -#define FLASH_CFG_READ_MD_SHIFT 0 -#define FLASH_CFG_READ_MD_WIDTH 1 -#define FLASH_CFG_READ_MD_MASK (((1U << FLASH_CFG_READ_MD_WIDTH) - 1U) << FLASH_CFG_READ_MD_SHIFT) -#define FLASH_CFG_READ_MD_VALUE_1_CYCLE 0U -#define FLASH_CFG_READ_MD_BITS_1_CYCLE (FLASH_CFG_READ_MD_VALUE_1_CYCLE << FLASH_CFG_READ_MD_SHIFT) -#define FLASH_CFG_READ_MD_VALUE_2_CYCLE 1U -#define FLASH_CFG_READ_MD_BITS_2_CYCLE (FLASH_CFG_READ_MD_VALUE_2_CYCLE << FLASH_CFG_READ_MD_SHIFT) - -#define FLASH_CFG_NVR_SEL_SHIFT 1 -#define FLASH_CFG_NVR_SEL_WIDTH 1 -#define FLASH_CFG_NVR_SEL_MASK (((1U << FLASH_CFG_NVR_SEL_WIDTH) - 1U) << FLASH_CFG_NVR_SEL_SHIFT) -#define FLASH_CFG_NVR_SEL_VALUE_MAIN 0U -#define FLASH_CFG_NVR_SEL_BITS_MAIN (FLASH_CFG_NVR_SEL_VALUE_MAIN << FLASH_CFG_NVR_SEL_SHIFT) -#define FLASH_CFG_NVR_SEL_VALUE_NVR 1U -#define FLASH_CFG_NVR_SEL_BITS_NVR (FLASH_CFG_NVR_SEL_VALUE_NVR << FLASH_CFG_NVR_SEL_SHIFT) - -#define FLASH_CFG_MODE_SHIFT 2 -#define FLASH_CFG_MODE_WIDTH 3 -#define FLASH_CFG_MODE_MASK (((1U << FLASH_CFG_MODE_WIDTH) - 1U) << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_VALUE_READ_AHB 0U -#define FLASH_CFG_MODE_BITS_READ_AHB (FLASH_CFG_MODE_VALUE_READ_AHB << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_VALUE_PROGRAM 1U -#define FLASH_CFG_MODE_BITS_PROGRAM (FLASH_CFG_MODE_VALUE_PROGRAM << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_VALUE_ERASE 2U -#define FLASH_CFG_MODE_BITS_ERASE (FLASH_CFG_MODE_VALUE_ERASE << FLASH_CFG_MODE_SHIFT) -#define FLASH_CFG_MODE_VALUE_READ_APB 5U -#define FLASH_CFG_MODE_BITS_READ_APB (FLASH_CFG_MODE_VALUE_READ_APB << FLASH_CFG_MODE_SHIFT) - -#define FLASH_CFG_DEEP_PD_SHIFT 31 -#define FLASH_CFG_DEEP_PD_WIDTH 1 -#define FLASH_CFG_DEEP_PD_MASK (((1U << FLASH_CFG_DEEP_PD_WIDTH) - 1U) << FLASH_CFG_DEEP_PD_SHIFT) -#define FLASH_CFG_DEEP_PD_VALUE_NORMAL 0U -#define FLASH_CFG_DEEP_PD_BITS_NORMAL (FLASH_CFG_DEEP_PD_VALUE_NORMAL << FLASH_CFG_DEEP_PD_SHIFT) -#define FLASH_CFG_DEEP_PD_VALUE_LOW_POWER 1U -#define FLASH_CFG_DEEP_PD_BITS_LOW_POWER (FLASH_CFG_DEEP_PD_VALUE_LOW_POWER << FLASH_CFG_DEEP_PD_SHIFT) - -#define FLASH_ADDR_ADDR (FLASH_BASE_ADDR + 0x0004U) -#define FLASH_ADDR (*(volatile uint32_t *)FLASH_ADDR_ADDR) -#define FLASH_WDATA_ADDR (FLASH_BASE_ADDR + 0x0008U) -#define FLASH_WDATA (*(volatile uint32_t *)FLASH_WDATA_ADDR) -#define FLASH_RDATA_ADDR (FLASH_BASE_ADDR + 0x000CU) -#define FLASH_RDATA (*(volatile uint32_t *)FLASH_RDATA_ADDR) - -#define FLASH_START_ADDR (FLASH_BASE_ADDR + 0x0010U) -#define FLASH_START (*(volatile uint32_t *)FLASH_START_ADDR) -#define FLASH_START_START_SHIFT 0 -#define FLASH_START_START_WIDTH 1 -#define FLASH_START_START_MASK (((1U << FLASH_START_START_WIDTH) - 1U) << FLASH_START_START_SHIFT) -#define FLASH_START_START_VALUE_START 1U -#define FLASH_START_START_BITS_START (FLASH_START_START_VALUE_START << FLASH_START_START_SHIFT) - -#define FLASH_ST_ADDR (FLASH_BASE_ADDR + 0x0014U) -#define FLASH_ST (*(volatile uint32_t *)FLASH_ST_ADDR) -#define FLASH_ST_INIT_BUSY_SHIFT 0 -#define FLASH_ST_INIT_BUSY_WIDTH 1 -#define FLASH_ST_INIT_BUSY_MASK (((1U << FLASH_ST_INIT_BUSY_WIDTH) - 1U) << FLASH_ST_INIT_BUSY_SHIFT) -#define FLASH_ST_INIT_BUSY_VALUE_COMPLETE 0U -#define FLASH_ST_INIT_BUSY_BITS_COMPLETE (FLASH_ST_INIT_BUSY_VALUE_COMPLETE << FLASH_ST_INIT_BUSY_SHIFT) -#define FLASH_ST_INIT_BUSY_VALUE_BUSY 1U -#define FLASH_ST_INIT_BUSY_BITS_BUSY (FLASH_ST_INIT_BUSY_VALUE_BUSY << FLASH_ST_INIT_BUSY_SHIFT) - -#define FLASH_ST_BUSY_SHIFT 1 -#define FLASH_ST_BUSY_WIDTH 1 -#define FLASH_ST_BUSY_MASK (((1U << FLASH_ST_BUSY_WIDTH) - 1U) << FLASH_ST_BUSY_SHIFT) -#define FLASH_ST_BUSY_VALUE_READY 0U -#define FLASH_ST_BUSY_BITS_READY (FLASH_ST_BUSY_VALUE_READY << FLASH_ST_BUSY_SHIFT) -#define FLASH_ST_BUSY_VALUE_BUSY 1U -#define FLASH_ST_BUSY_BITS_BUSY (FLASH_ST_BUSY_VALUE_BUSY << FLASH_ST_BUSY_SHIFT) - -#define FLASH_ST_PROG_BUF_EMPTY_SHIFT 2 -#define FLASH_ST_PROG_BUF_EMPTY_WIDTH 1 -#define FLASH_ST_PROG_BUF_EMPTY_MASK (((1U << FLASH_ST_PROG_BUF_EMPTY_WIDTH) - 1U) << FLASH_ST_PROG_BUF_EMPTY_SHIFT) -#define FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY 0U -#define FLASH_ST_PROG_BUF_EMPTY_BITS_NOT_EMPTY (FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT) -#define FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY 1U -#define FLASH_ST_PROG_BUF_EMPTY_BITS_EMPTY (FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT) - -#define FLASH_LOCK_ADDR (FLASH_BASE_ADDR + 0x0018U) -#define FLASH_LOCK (*(volatile uint32_t *)FLASH_LOCK_ADDR) -#define FLASH_LOCK_LOCK_SHIFT 0 -#define FLASH_LOCK_LOCK_WIDTH 8 -#define FLASH_LOCK_LOCK_MASK (((1U << FLASH_LOCK_LOCK_WIDTH) - 1U) << FLASH_LOCK_LOCK_SHIFT) -#define FLASH_LOCK_LOCK_VALUE_LOCK 85U -#define FLASH_LOCK_LOCK_BITS_LOCK (FLASH_LOCK_LOCK_VALUE_LOCK << FLASH_LOCK_LOCK_SHIFT) - -#define FLASH_UNLOCK_ADDR (FLASH_BASE_ADDR + 0x001CU) -#define FLASH_UNLOCK (*(volatile uint32_t *)FLASH_UNLOCK_ADDR) -#define FLASH_UNLOCK_UNLOCK_SHIFT 0 -#define FLASH_UNLOCK_UNLOCK_WIDTH 8 -#define FLASH_UNLOCK_UNLOCK_MASK (((1U << FLASH_UNLOCK_UNLOCK_WIDTH) - 1U) << FLASH_UNLOCK_UNLOCK_SHIFT) -#define FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK 170U -#define FLASH_UNLOCK_UNLOCK_BITS_UNLOCK (FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK << FLASH_UNLOCK_UNLOCK_SHIFT) - -#define FLASH_MASK_ADDR (FLASH_BASE_ADDR + 0x0020U) -#define FLASH_MASK (*(volatile uint32_t *)FLASH_MASK_ADDR) -#define FLASH_MASK_SEL_SHIFT 0 -#define FLASH_MASK_SEL_WIDTH 2 -#define FLASH_MASK_SEL_MASK (((1U << FLASH_MASK_SEL_WIDTH) - 1U) << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_VALUE_NONE 0U -#define FLASH_MASK_SEL_BITS_NONE (FLASH_MASK_SEL_VALUE_NONE << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_VALUE_2KB 1U -#define FLASH_MASK_SEL_BITS_2KB (FLASH_MASK_SEL_VALUE_2KB << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_VALUE_4KB 2U -#define FLASH_MASK_SEL_BITS_4KB (FLASH_MASK_SEL_VALUE_4KB << FLASH_MASK_SEL_SHIFT) -#define FLASH_MASK_SEL_VALUE_8KB 3U -#define FLASH_MASK_SEL_BITS_8KB (FLASH_MASK_SEL_VALUE_8KB << FLASH_MASK_SEL_SHIFT) - -#define FLASH_MASK_LOCK_SHIFT 2 -#define FLASH_MASK_LOCK_WIDTH 1 -#define FLASH_MASK_LOCK_MASK (((1U << FLASH_MASK_LOCK_WIDTH) - 1U) << FLASH_MASK_LOCK_SHIFT) -#define FLASH_MASK_LOCK_VALUE_NOT_SET 0U -#define FLASH_MASK_LOCK_BITS_NOT_SET (FLASH_MASK_LOCK_VALUE_NOT_SET << FLASH_MASK_LOCK_SHIFT) -#define FLASH_MASK_LOCK_VALUE_SET 1U -#define FLASH_MASK_LOCK_BITS_SET (FLASH_MASK_LOCK_VALUE_SET << FLASH_MASK_LOCK_SHIFT) - -#define FLASH_ERASETIME_ADDR (FLASH_BASE_ADDR + 0x0024U) -#define FLASH_ERASETIME (*(volatile uint32_t *)FLASH_ERASETIME_ADDR) -#define FLASH_ERASETIME_TERASE_SHIFT 0 -#define FLASH_ERASETIME_TERASE_WIDTH 19 -#define FLASH_ERASETIME_TERASE_MASK (((1U << FLASH_ERASETIME_TERASE_WIDTH) - 1U) << FLASH_ERASETIME_TERASE_SHIFT) -#define FLASH_ERASETIME_TRCV_SHIFT 19 -#define FLASH_ERASETIME_TRCV_WIDTH 12 -#define FLASH_ERASETIME_TRCV_MASK (((1U << FLASH_ERASETIME_TRCV_WIDTH) - 1U) << FLASH_ERASETIME_TRCV_SHIFT) - -#define FLASH_PROGTIME_ADDR (FLASH_BASE_ADDR + 0x0028U) -#define FLASH_PROGTIME (*(volatile uint32_t *)FLASH_PROGTIME_ADDR) -#define FLASH_PROGTIME_TPROG_SHIFT 0 -#define FLASH_PROGTIME_TPROG_WIDTH 11 -#define FLASH_PROGTIME_TPROG_MASK (((1U << FLASH_PROGTIME_TPROG_WIDTH) - 1U) << FLASH_PROGTIME_TPROG_SHIFT) -#define FLASH_PROGTIME_TPGS_SHIFT 11 -#define FLASH_PROGTIME_TPGS_WIDTH 11 -#define FLASH_PROGTIME_TPGS_MASK (((1U << FLASH_PROGTIME_TPGS_WIDTH) - 1U) << FLASH_PROGTIME_TPGS_SHIFT) - - -#endif - diff --git a/App/bsp/dp32g030/gpio.h b/App/bsp/dp32g030/gpio.h deleted file mode 100644 index 6c9bbcb3..00000000 --- a/App/bsp/dp32g030/gpio.h +++ /dev/null @@ -1,176 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_GPIO_H -#define HARDWARE_DP32G030_GPIO_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- GPIOA -------- */ -#define GPIOA_BASE_ADDR 0x40060000U -#define GPIOA_BASE_SIZE 0x00000800U -#define GPIOA ((volatile GPIO_Bank_t *)GPIOA_BASE_ADDR) - -/* -------- GPIOB -------- */ -#define GPIOB_BASE_ADDR 0x40060800U -#define GPIOB_BASE_SIZE 0x00000800U -#define GPIOB ((volatile GPIO_Bank_t *)GPIOB_BASE_ADDR) - -/* -------- GPIOC -------- */ -#define GPIOC_BASE_ADDR 0x40061000U -#define GPIOC_BASE_SIZE 0x00000800U -#define GPIOC ((volatile GPIO_Bank_t *)GPIOC_BASE_ADDR) - -/* -------- GPIO -------- */ - -typedef struct { - uint32_t DATA; - uint32_t DIR; -} GPIO_Bank_t; - -#define GPIO_DIR_0_SHIFT 0 -#define GPIO_DIR_0_WIDTH 1 -#define GPIO_DIR_0_MASK (((1U << GPIO_DIR_0_WIDTH) - 1U) << GPIO_DIR_0_SHIFT) -#define GPIO_DIR_0_VALUE_INPUT 0U -#define GPIO_DIR_0_BITS_INPUT (GPIO_DIR_0_VALUE_INPUT << GPIO_DIR_0_SHIFT) -#define GPIO_DIR_0_VALUE_OUTPUT 1U -#define GPIO_DIR_0_BITS_OUTPUT (GPIO_DIR_0_VALUE_OUTPUT << GPIO_DIR_0_SHIFT) - -#define GPIO_DIR_1_SHIFT 1 -#define GPIO_DIR_1_WIDTH 1 -#define GPIO_DIR_1_MASK (((1U << GPIO_DIR_1_WIDTH) - 1U) << GPIO_DIR_1_SHIFT) -#define GPIO_DIR_1_VALUE_INPUT 0U -#define GPIO_DIR_1_BITS_INPUT (GPIO_DIR_1_VALUE_INPUT << GPIO_DIR_1_SHIFT) -#define GPIO_DIR_1_VALUE_OUTPUT 1U -#define GPIO_DIR_1_BITS_OUTPUT (GPIO_DIR_1_VALUE_OUTPUT << GPIO_DIR_1_SHIFT) - -#define GPIO_DIR_2_SHIFT 2 -#define GPIO_DIR_2_WIDTH 1 -#define GPIO_DIR_2_MASK (((1U << GPIO_DIR_2_WIDTH) - 1U) << GPIO_DIR_2_SHIFT) -#define GPIO_DIR_2_VALUE_INPUT 0U -#define GPIO_DIR_2_BITS_INPUT (GPIO_DIR_2_VALUE_INPUT << GPIO_DIR_2_SHIFT) -#define GPIO_DIR_2_VALUE_OUTPUT 1U -#define GPIO_DIR_2_BITS_OUTPUT (GPIO_DIR_2_VALUE_OUTPUT << GPIO_DIR_2_SHIFT) - -#define GPIO_DIR_3_SHIFT 3 -#define GPIO_DIR_3_WIDTH 1 -#define GPIO_DIR_3_MASK (((1U << GPIO_DIR_3_WIDTH) - 1U) << GPIO_DIR_3_SHIFT) -#define GPIO_DIR_3_VALUE_INPUT 0U -#define GPIO_DIR_3_BITS_INPUT (GPIO_DIR_3_VALUE_INPUT << GPIO_DIR_3_SHIFT) -#define GPIO_DIR_3_VALUE_OUTPUT 1U -#define GPIO_DIR_3_BITS_OUTPUT (GPIO_DIR_3_VALUE_OUTPUT << GPIO_DIR_3_SHIFT) - -#define GPIO_DIR_4_SHIFT 4 -#define GPIO_DIR_4_WIDTH 1 -#define GPIO_DIR_4_MASK (((1U << GPIO_DIR_4_WIDTH) - 1U) << GPIO_DIR_4_SHIFT) -#define GPIO_DIR_4_VALUE_INPUT 0U -#define GPIO_DIR_4_BITS_INPUT (GPIO_DIR_4_VALUE_INPUT << GPIO_DIR_4_SHIFT) -#define GPIO_DIR_4_VALUE_OUTPUT 1U -#define GPIO_DIR_4_BITS_OUTPUT (GPIO_DIR_4_VALUE_OUTPUT << GPIO_DIR_4_SHIFT) - -#define GPIO_DIR_5_SHIFT 5 -#define GPIO_DIR_5_WIDTH 1 -#define GPIO_DIR_5_MASK (((1U << GPIO_DIR_5_WIDTH) - 1U) << GPIO_DIR_5_SHIFT) -#define GPIO_DIR_5_VALUE_INPUT 0U -#define GPIO_DIR_5_BITS_INPUT (GPIO_DIR_5_VALUE_INPUT << GPIO_DIR_5_SHIFT) -#define GPIO_DIR_5_VALUE_OUTPUT 1U -#define GPIO_DIR_5_BITS_OUTPUT (GPIO_DIR_5_VALUE_OUTPUT << GPIO_DIR_5_SHIFT) - -#define GPIO_DIR_6_SHIFT 6 -#define GPIO_DIR_6_WIDTH 1 -#define GPIO_DIR_6_MASK (((1U << GPIO_DIR_6_WIDTH) - 1U) << GPIO_DIR_6_SHIFT) -#define GPIO_DIR_6_VALUE_INPUT 0U -#define GPIO_DIR_6_BITS_INPUT (GPIO_DIR_6_VALUE_INPUT << GPIO_DIR_6_SHIFT) -#define GPIO_DIR_6_VALUE_OUTPUT 1U -#define GPIO_DIR_6_BITS_OUTPUT (GPIO_DIR_6_VALUE_OUTPUT << GPIO_DIR_6_SHIFT) - -#define GPIO_DIR_7_SHIFT 7 -#define GPIO_DIR_7_WIDTH 1 -#define GPIO_DIR_7_MASK (((1U << GPIO_DIR_7_WIDTH) - 1U) << GPIO_DIR_7_SHIFT) -#define GPIO_DIR_7_VALUE_INPUT 0U -#define GPIO_DIR_7_BITS_INPUT (GPIO_DIR_7_VALUE_INPUT << GPIO_DIR_7_SHIFT) -#define GPIO_DIR_7_VALUE_OUTPUT 1U -#define GPIO_DIR_7_BITS_OUTPUT (GPIO_DIR_7_VALUE_OUTPUT << GPIO_DIR_7_SHIFT) - -#define GPIO_DIR_8_SHIFT 8 -#define GPIO_DIR_8_WIDTH 1 -#define GPIO_DIR_8_MASK (((1U << GPIO_DIR_8_WIDTH) - 1U) << GPIO_DIR_8_SHIFT) -#define GPIO_DIR_8_VALUE_INPUT 0U -#define GPIO_DIR_8_BITS_INPUT (GPIO_DIR_8_VALUE_INPUT << GPIO_DIR_8_SHIFT) -#define GPIO_DIR_8_VALUE_OUTPUT 1U -#define GPIO_DIR_8_BITS_OUTPUT (GPIO_DIR_8_VALUE_OUTPUT << GPIO_DIR_8_SHIFT) - -#define GPIO_DIR_9_SHIFT 9 -#define GPIO_DIR_9_WIDTH 1 -#define GPIO_DIR_9_MASK (((1U << GPIO_DIR_9_WIDTH) - 1U) << GPIO_DIR_9_SHIFT) -#define GPIO_DIR_9_VALUE_INPUT 0U -#define GPIO_DIR_9_BITS_INPUT (GPIO_DIR_9_VALUE_INPUT << GPIO_DIR_9_SHIFT) -#define GPIO_DIR_9_VALUE_OUTPUT 1U -#define GPIO_DIR_9_BITS_OUTPUT (GPIO_DIR_9_VALUE_OUTPUT << GPIO_DIR_9_SHIFT) - -#define GPIO_DIR_10_SHIFT 10 -#define GPIO_DIR_10_WIDTH 1 -#define GPIO_DIR_10_MASK (((1U << GPIO_DIR_10_WIDTH) - 1U) << GPIO_DIR_10_SHIFT) -#define GPIO_DIR_10_VALUE_INPUT 0U -#define GPIO_DIR_10_BITS_INPUT (GPIO_DIR_10_VALUE_INPUT << GPIO_DIR_10_SHIFT) -#define GPIO_DIR_10_VALUE_OUTPUT 1U -#define GPIO_DIR_10_BITS_OUTPUT (GPIO_DIR_10_VALUE_OUTPUT << GPIO_DIR_10_SHIFT) - -#define GPIO_DIR_11_SHIFT 11 -#define GPIO_DIR_11_WIDTH 1 -#define GPIO_DIR_11_MASK (((1U << GPIO_DIR_11_WIDTH) - 1U) << GPIO_DIR_11_SHIFT) -#define GPIO_DIR_11_VALUE_INPUT 0U -#define GPIO_DIR_11_BITS_INPUT (GPIO_DIR_11_VALUE_INPUT << GPIO_DIR_11_SHIFT) -#define GPIO_DIR_11_VALUE_OUTPUT 1U -#define GPIO_DIR_11_BITS_OUTPUT (GPIO_DIR_11_VALUE_OUTPUT << GPIO_DIR_11_SHIFT) - -#define GPIO_DIR_12_SHIFT 12 -#define GPIO_DIR_12_WIDTH 1 -#define GPIO_DIR_12_MASK (((1U << GPIO_DIR_12_WIDTH) - 1U) << GPIO_DIR_12_SHIFT) -#define GPIO_DIR_12_VALUE_INPUT 0U -#define GPIO_DIR_12_BITS_INPUT (GPIO_DIR_12_VALUE_INPUT << GPIO_DIR_12_SHIFT) -#define GPIO_DIR_12_VALUE_OUTPUT 1U -#define GPIO_DIR_12_BITS_OUTPUT (GPIO_DIR_12_VALUE_OUTPUT << GPIO_DIR_12_SHIFT) - -#define GPIO_DIR_13_SHIFT 13 -#define GPIO_DIR_13_WIDTH 1 -#define GPIO_DIR_13_MASK (((1U << GPIO_DIR_13_WIDTH) - 1U) << GPIO_DIR_13_SHIFT) -#define GPIO_DIR_13_VALUE_INPUT 0U -#define GPIO_DIR_13_BITS_INPUT (GPIO_DIR_13_VALUE_INPUT << GPIO_DIR_13_SHIFT) -#define GPIO_DIR_13_VALUE_OUTPUT 1U -#define GPIO_DIR_13_BITS_OUTPUT (GPIO_DIR_13_VALUE_OUTPUT << GPIO_DIR_13_SHIFT) - -#define GPIO_DIR_14_SHIFT 14 -#define GPIO_DIR_14_WIDTH 1 -#define GPIO_DIR_14_MASK (((1U << GPIO_DIR_14_WIDTH) - 1U) << GPIO_DIR_14_SHIFT) -#define GPIO_DIR_14_VALUE_INPUT 0U -#define GPIO_DIR_14_BITS_INPUT (GPIO_DIR_14_VALUE_INPUT << GPIO_DIR_14_SHIFT) -#define GPIO_DIR_14_VALUE_OUTPUT 1U -#define GPIO_DIR_14_BITS_OUTPUT (GPIO_DIR_14_VALUE_OUTPUT << GPIO_DIR_14_SHIFT) - -#define GPIO_DIR_15_SHIFT 15 -#define GPIO_DIR_15_WIDTH 1 -#define GPIO_DIR_15_MASK (((1U << GPIO_DIR_15_WIDTH) - 1U) << GPIO_DIR_15_SHIFT) -#define GPIO_DIR_15_VALUE_INPUT 0U -#define GPIO_DIR_15_BITS_INPUT (GPIO_DIR_15_VALUE_INPUT << GPIO_DIR_15_SHIFT) -#define GPIO_DIR_15_VALUE_OUTPUT 1U -#define GPIO_DIR_15_BITS_OUTPUT (GPIO_DIR_15_VALUE_OUTPUT << GPIO_DIR_15_SHIFT) - - -#endif - diff --git a/App/bsp/dp32g030/irq.h b/App/bsp/dp32g030/irq.h deleted file mode 100644 index 1cbd7245..00000000 --- a/App/bsp/dp32g030/irq.h +++ /dev/null @@ -1,40 +0,0 @@ -#ifndef DP32G030_IRQ_H -#define DP32G030_IRQ_H - -enum { - DP32_WWDT_IRQn = 0, - DP32_IWDT_IRQn, - DP32_RTC_IRQn, - DP32_DMA_IRQn, - DP32_SARADC_IRQn, - DP32_TIMER_BASE0_IRQn, - DP32_TIMER_BASE1_IRQn, - DP32_TIMER_PLUS0_IRQn, - DP32_TIMER_PLUS1_IRQn, - DP32_PWM_BASE0_IRQn, - DP32_PWM_BASE1_IRQn, - DP32_PWM_PLUS0_IRQn, - DP32_PWM_PLUS1_IRQn, - DP32_UART0_IRQn, - DP32_UART1_IRQn, - DP32_UART2_IRQn, - DP32_SPI0_IRQn, - DP32_SPI1_IRQn, - DP32_IIC0_IRQn, - DP32_IIC1_IRQn, - DP32_CMP_IRQn, - DP32_TIMER_BASE2_IRQn, - DP32_GPIOA5_IRQn, - DP32_GPIOA6_IRQn, - DP32_GPIOA7_IRQn, - DP32_GPIOB0_IRQn, - DP32_GPIOB1_IRQn, - DP32_GPIOC0_IRQn, - DP32_GPIOC1_IRQn, - DP32_GPIOA_IRQn, - DP32_GPIOB_IRQn, - DP32_GPIOC_IRQn, -}; - -#endif - diff --git a/App/bsp/dp32g030/pmu.h b/App/bsp/dp32g030/pmu.h deleted file mode 100644 index 7727474a..00000000 --- a/App/bsp/dp32g030/pmu.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_PMU_H -#define HARDWARE_DP32G030_PMU_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- PMU -------- */ -#define PMU_BASE_ADDR 0x40000800U -#define PMU_BASE_SIZE 0x00000800U - -#define PMU_SRC_CFG_ADDR (PMU_BASE_ADDR + 0x0010U) -#define PMU_SRC_CFG (*(volatile uint32_t *)PMU_SRC_CFG_ADDR) -#define PMU_SRC_CFG_RCHF_EN_SHIFT 0 -#define PMU_SRC_CFG_RCHF_EN_WIDTH 1 -#define PMU_SRC_CFG_RCHF_EN_MASK (((1U << PMU_SRC_CFG_RCHF_EN_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_EN_SHIFT) -#define PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE 0U -#define PMU_SRC_CFG_RCHF_EN_BITS_DISABLE (PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE << PMU_SRC_CFG_RCHF_EN_SHIFT) -#define PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE 1U -#define PMU_SRC_CFG_RCHF_EN_BITS_ENABLE (PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE << PMU_SRC_CFG_RCHF_EN_SHIFT) - -#define PMU_SRC_CFG_RCHF_SEL_SHIFT 1 -#define PMU_SRC_CFG_RCHF_SEL_WIDTH 1 -#define PMU_SRC_CFG_RCHF_SEL_MASK (((1U << PMU_SRC_CFG_RCHF_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_SEL_SHIFT) -#define PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ 0U -#define PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT) -#define PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ 1U -#define PMU_SRC_CFG_RCHF_SEL_BITS_24MHZ (PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT) - -#define PMU_TRIM_POW0_ADDR (PMU_BASE_ADDR + 0x0020U) -#define PMU_TRIM_POW0 (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR) -#define PMU_TRIM_POW1_ADDR (PMU_BASE_ADDR + 0x0024U) -#define PMU_TRIM_POW1 (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR) -#define PMU_TRIM_POW2_ADDR (PMU_BASE_ADDR + 0x0028U) -#define PMU_TRIM_POW2 (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR) -#define PMU_TRIM_POW3_ADDR (PMU_BASE_ADDR + 0x002CU) -#define PMU_TRIM_POW3 (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR) -#define PMU_TRIM_RCHF_ADDR (PMU_BASE_ADDR + 0x0030U) -#define PMU_TRIM_RCHF (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR) -#define PMU_TRIM_RCLF_ADDR (PMU_BASE_ADDR + 0x0034U) -#define PMU_TRIM_RCLF (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR) -#define PMU_TRIM_OPA_ADDR (PMU_BASE_ADDR + 0x0038U) -#define PMU_TRIM_OPA (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR) -#define PMU_TRIM_PLL_ADDR (PMU_BASE_ADDR + 0x003CU) -#define PMU_TRIM_PLL (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR) - - -#endif - diff --git a/App/bsp/dp32g030/portcon.h b/App/bsp/dp32g030/portcon.h deleted file mode 100644 index d77507bf..00000000 --- a/App/bsp/dp32g030/portcon.h +++ /dev/null @@ -1,2174 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_PORTCON_H -#define HARDWARE_DP32G030_PORTCON_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- PORTCON -------- */ -#define PORTCON_BASE_ADDR 0x400B0000U -#define PORTCON_BASE_SIZE 0x00000800U - -#define PORTCON_PORTA_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0000U) -#define PORTCON_PORTA_SEL0 (*(volatile uint32_t *)PORTCON_PORTA_SEL0_ADDR) -#define PORTCON_PORTA_SEL0_A0_SHIFT 0 -#define PORTCON_PORTA_SEL0_A0_WIDTH 4 -#define PORTCON_PORTA_SEL0_A0_MASK (((1U << PORTCON_PORTA_SEL0_A0_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0 0U -#define PORTCON_PORTA_SEL0_A0_BITS_GPIOA0 (PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0 << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0 1U -#define PORTCON_PORTA_SEL0_A0_BITS_PWMP1_PLUS0 (PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0 << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1 2U -#define PORTCON_PORTA_SEL0_A0_BITS_PWMP0_PLUS1 (PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1 << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_VALUE_TM 3U -#define PORTCON_PORTA_SEL0_A0_BITS_TM (PORTCON_PORTA_SEL0_A0_VALUE_TM << PORTCON_PORTA_SEL0_A0_SHIFT) -#define PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0 4U -#define PORTCON_PORTA_SEL0_A0_BITS_WAKEUP0 (PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0 << PORTCON_PORTA_SEL0_A0_SHIFT) - -#define PORTCON_PORTA_SEL0_A1_SHIFT 4 -#define PORTCON_PORTA_SEL0_A1_WIDTH 4 -#define PORTCON_PORTA_SEL0_A1_MASK (((1U << PORTCON_PORTA_SEL0_A1_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A1_SHIFT) -#define PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1 0U -#define PORTCON_PORTA_SEL0_A1_BITS_GPIOA1 (PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1 << PORTCON_PORTA_SEL0_A1_SHIFT) -#define PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI 1U -#define PORTCON_PORTA_SEL0_A1_BITS_XTAL_XI (PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI << PORTCON_PORTA_SEL0_A1_SHIFT) - -#define PORTCON_PORTA_SEL0_A2_SHIFT 8 -#define PORTCON_PORTA_SEL0_A2_WIDTH 4 -#define PORTCON_PORTA_SEL0_A2_MASK (((1U << PORTCON_PORTA_SEL0_A2_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A2_SHIFT) -#define PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2 0U -#define PORTCON_PORTA_SEL0_A2_BITS_GPIOA2 (PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2 << PORTCON_PORTA_SEL0_A2_SHIFT) -#define PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO 1U -#define PORTCON_PORTA_SEL0_A2_BITS_XTAL_XO (PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO << PORTCON_PORTA_SEL0_A2_SHIFT) - -#define PORTCON_PORTA_SEL0_A3_SHIFT 12 -#define PORTCON_PORTA_SEL0_A3_WIDTH 4 -#define PORTCON_PORTA_SEL0_A3_MASK (((1U << PORTCON_PORTA_SEL0_A3_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A3_SHIFT) -#define PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3 0U -#define PORTCON_PORTA_SEL0_A3_BITS_GPIOA3 (PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3 << PORTCON_PORTA_SEL0_A3_SHIFT) -#define PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN 1U -#define PORTCON_PORTA_SEL0_A3_BITS_CMP0_VN (PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN << PORTCON_PORTA_SEL0_A3_SHIFT) -#define PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI 2U -#define PORTCON_PORTA_SEL0_A3_BITS_XTAH_XI (PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI << PORTCON_PORTA_SEL0_A3_SHIFT) - -#define PORTCON_PORTA_SEL0_A4_SHIFT 16 -#define PORTCON_PORTA_SEL0_A4_WIDTH 4 -#define PORTCON_PORTA_SEL0_A4_MASK (((1U << PORTCON_PORTA_SEL0_A4_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A4_SHIFT) -#define PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4 0U -#define PORTCON_PORTA_SEL0_A4_BITS_GPIOA4 (PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4 << PORTCON_PORTA_SEL0_A4_SHIFT) -#define PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP 1U -#define PORTCON_PORTA_SEL0_A4_BITS_CMP0_VP (PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP << PORTCON_PORTA_SEL0_A4_SHIFT) -#define PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO 2U -#define PORTCON_PORTA_SEL0_A4_BITS_XTAH_XO (PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO << PORTCON_PORTA_SEL0_A4_SHIFT) - -#define PORTCON_PORTA_SEL0_A5_SHIFT 20 -#define PORTCON_PORTA_SEL0_A5_WIDTH 4 -#define PORTCON_PORTA_SEL0_A5_MASK (((1U << PORTCON_PORTA_SEL0_A5_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5 0U -#define PORTCON_PORTA_SEL0_A5_BITS_GPIOA5 (PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5 << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS 1U -#define PORTCON_PORTA_SEL0_A5_BITS_UART1_CTS (PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1 2U -#define PORTCON_PORTA_SEL0_A5_BITS_PWMP1_PLUS1 (PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1 << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0 3U -#define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L 4U -#define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1 5U -#define PORTCON_PORTA_SEL0_A5_BITS_WAKEUP1 (PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1 << PORTCON_PORTA_SEL0_A5_SHIFT) -#define PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1 6U -#define PORTCON_PORTA_SEL0_A5_BITS_SARADC_CH1 (PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A5_SHIFT) - -#define PORTCON_PORTA_SEL0_A6_SHIFT 24 -#define PORTCON_PORTA_SEL0_A6_WIDTH 4 -#define PORTCON_PORTA_SEL0_A6_MASK (((1U << PORTCON_PORTA_SEL0_A6_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6 0U -#define PORTCON_PORTA_SEL0_A6_BITS_GPIOA6 (PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6 << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS 1U -#define PORTCON_PORTA_SEL0_A6_BITS_UART1_RTS (PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1 2U -#define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H 3U -#define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1 4U -#define PORTCON_PORTA_SEL0_A6_BITS_SARADC_CH1 (PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A6_SHIFT) -#define PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT 5U -#define PORTCON_PORTA_SEL0_A6_BITS_OPA0_OUT (PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT << PORTCON_PORTA_SEL0_A6_SHIFT) - -#define PORTCON_PORTA_SEL0_A7_SHIFT 28 -#define PORTCON_PORTA_SEL0_A7_WIDTH 4 -#define PORTCON_PORTA_SEL0_A7_MASK (((1U << PORTCON_PORTA_SEL0_A7_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7 0U -#define PORTCON_PORTA_SEL0_A7_BITS_GPIOA7 (PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7 << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX 1U -#define PORTCON_PORTA_SEL0_A7_BITS_UART1_TX (PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0 2U -#define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_IN0 (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L 3U -#define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_OUT_L (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2 4U -#define PORTCON_PORTA_SEL0_A7_BITS_SARADC_CH2 (PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2 << PORTCON_PORTA_SEL0_A7_SHIFT) -#define PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP 5U -#define PORTCON_PORTA_SEL0_A7_BITS_OPA0_VP (PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP << PORTCON_PORTA_SEL0_A7_SHIFT) - -#define PORTCON_PORTA_SEL1_ADDR (PORTCON_BASE_ADDR + 0x0004U) -#define PORTCON_PORTA_SEL1 (*(volatile uint32_t *)PORTCON_PORTA_SEL1_ADDR) -#define PORTCON_PORTA_SEL1_A8_SHIFT 0 -#define PORTCON_PORTA_SEL1_A8_WIDTH 4 -#define PORTCON_PORTA_SEL1_A8_MASK (((1U << PORTCON_PORTA_SEL1_A8_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8 0U -#define PORTCON_PORTA_SEL1_A8_BITS_GPIOA8 (PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8 << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX 1U -#define PORTCON_PORTA_SEL1_A8_BITS_UART1_RX (PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1 2U -#define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_IN1 (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H 3U -#define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_OUT_H (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3 4U -#define PORTCON_PORTA_SEL1_A8_BITS_SARADC_CH3 (PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3 << PORTCON_PORTA_SEL1_A8_SHIFT) -#define PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN 5U -#define PORTCON_PORTA_SEL1_A8_BITS_OPA0_VN (PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN << PORTCON_PORTA_SEL1_A8_SHIFT) - -#define PORTCON_PORTA_SEL1_A9_SHIFT 4 -#define PORTCON_PORTA_SEL1_A9_WIDTH 4 -#define PORTCON_PORTA_SEL1_A9_MASK (((1U << PORTCON_PORTA_SEL1_A9_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9 0U -#define PORTCON_PORTA_SEL1_A9_BITS_GPIOA9 (PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9 << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN 1U -#define PORTCON_PORTA_SEL1_A9_BITS_SPI0_SSN (PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0 2U -#define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L 3U -#define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_VALUE_TM 4U -#define PORTCON_PORTA_SEL1_A9_BITS_TM (PORTCON_PORTA_SEL1_A9_VALUE_TM << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4 5U -#define PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4 (PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4 << PORTCON_PORTA_SEL1_A9_SHIFT) -#define PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN 6U -#define PORTCON_PORTA_SEL1_A9_BITS_CMP1_VN (PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN << PORTCON_PORTA_SEL1_A9_SHIFT) - -#define PORTCON_PORTA_SEL1_A10_SHIFT 8 -#define PORTCON_PORTA_SEL1_A10_WIDTH 4 -#define PORTCON_PORTA_SEL1_A10_MASK (((1U << PORTCON_PORTA_SEL1_A10_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10 0U -#define PORTCON_PORTA_SEL1_A10_BITS_GPIOA10 (PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10 << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK 1U -#define PORTCON_PORTA_SEL1_A10_BITS_SPI0_CLK (PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5 2U -#define PORTCON_PORTA_SEL1_A10_BITS_SARADC_CH5 (PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5 << PORTCON_PORTA_SEL1_A10_SHIFT) -#define PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP 3U -#define PORTCON_PORTA_SEL1_A10_BITS_CMP1_VP (PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP << PORTCON_PORTA_SEL1_A10_SHIFT) - -#define PORTCON_PORTA_SEL1_A11_SHIFT 12 -#define PORTCON_PORTA_SEL1_A11_WIDTH 4 -#define PORTCON_PORTA_SEL1_A11_MASK (((1U << PORTCON_PORTA_SEL1_A11_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11 0U -#define PORTCON_PORTA_SEL1_A11_BITS_GPIOA11 (PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11 << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO 1U -#define PORTCON_PORTA_SEL1_A11_BITS_SPI0_MISO (PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0 2U -#define PORTCON_PORTA_SEL1_A11_BITS_PWMB0_CH0 (PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0 << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0 3U -#define PORTCON_PORTA_SEL1_A11_BITS_PWMP0_BRAKE0 (PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0 << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1 4U -#define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H 5U -#define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A11_SHIFT) -#define PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6 6U -#define PORTCON_PORTA_SEL1_A11_BITS_SARADC_CH6 (PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6 << PORTCON_PORTA_SEL1_A11_SHIFT) - -#define PORTCON_PORTA_SEL1_A12_SHIFT 16 -#define PORTCON_PORTA_SEL1_A12_WIDTH 4 -#define PORTCON_PORTA_SEL1_A12_MASK (((1U << PORTCON_PORTA_SEL1_A12_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12 0U -#define PORTCON_PORTA_SEL1_A12_BITS_GPIOA12 (PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12 << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI 1U -#define PORTCON_PORTA_SEL1_A12_BITS_SPI0_MOSI (PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1 2U -#define PORTCON_PORTA_SEL1_A12_BITS_PWMB0_CH1 (PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1 << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N 3U -#define PORTCON_PORTA_SEL1_A12_BITS_PWMP0_CH0N (PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0 4U -#define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_IN0 (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L 5U -#define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_OUT_L (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL1_A12_SHIFT) -#define PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7 6U -#define PORTCON_PORTA_SEL1_A12_BITS_SARADC_CH7 (PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7 << PORTCON_PORTA_SEL1_A12_SHIFT) - -#define PORTCON_PORTA_SEL1_A13_SHIFT 20 -#define PORTCON_PORTA_SEL1_A13_WIDTH 4 -#define PORTCON_PORTA_SEL1_A13_MASK (((1U << PORTCON_PORTA_SEL1_A13_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13 0U -#define PORTCON_PORTA_SEL1_A13_BITS_GPIOA13 (PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13 << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2 1U -#define PORTCON_PORTA_SEL1_A13_BITS_PWMB0_CH2 (PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2 << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N 2U -#define PORTCON_PORTA_SEL1_A13_BITS_PWMP0_CH1N (PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1 3U -#define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_IN1 (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H 4U -#define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_OUT_H (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A13_SHIFT) -#define PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8 5U -#define PORTCON_PORTA_SEL1_A13_BITS_SARADC_CH8 (PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8 << PORTCON_PORTA_SEL1_A13_SHIFT) - -#define PORTCON_PORTA_SEL1_A14_SHIFT 24 -#define PORTCON_PORTA_SEL1_A14_WIDTH 4 -#define PORTCON_PORTA_SEL1_A14_MASK (((1U << PORTCON_PORTA_SEL1_A14_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14 0U -#define PORTCON_PORTA_SEL1_A14_BITS_GPIOA14 (PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14 << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0 1U -#define PORTCON_PORTA_SEL1_A14_BITS_PWMB1_CH0 (PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0 << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N 2U -#define PORTCON_PORTA_SEL1_A14_BITS_PWMP0_CH2N (PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0 3U -#define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_IN0 (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L 4U -#define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_OUT_L (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A14_SHIFT) -#define PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9 5U -#define PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9 (PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9 << PORTCON_PORTA_SEL1_A14_SHIFT) - -#define PORTCON_PORTA_SEL1_A15_SHIFT 28 -#define PORTCON_PORTA_SEL1_A15_WIDTH 4 -#define PORTCON_PORTA_SEL1_A15_MASK (((1U << PORTCON_PORTA_SEL1_A15_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15 0U -#define PORTCON_PORTA_SEL1_A15_BITS_GPIOA15 (PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15 << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1 1U -#define PORTCON_PORTA_SEL1_A15_BITS_PWMB1_CH1 (PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1 << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0 2U -#define PORTCON_PORTA_SEL1_A15_BITS_PWMP0_CH0 (PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0 << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1 3U -#define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_IN1 (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A15_SHIFT) -#define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H 4U -#define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_OUT_H (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A15_SHIFT) - -#define PORTCON_PORTB_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0008U) -#define PORTCON_PORTB_SEL0 (*(volatile uint32_t *)PORTCON_PORTB_SEL0_ADDR) -#define PORTCON_PORTB_SEL0_B0_SHIFT 0 -#define PORTCON_PORTB_SEL0_B0_WIDTH 4 -#define PORTCON_PORTB_SEL0_B0_MASK (((1U << PORTCON_PORTB_SEL0_B0_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0 0U -#define PORTCON_PORTB_SEL0_B0_BITS_GPIOB0 (PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0 << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX 1U -#define PORTCON_PORTB_SEL0_B0_BITS_UART2_TX (PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL 2U -#define PORTCON_PORTB_SEL0_B0_BITS_IIC0_SCL (PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2 3U -#define PORTCON_PORTB_SEL0_B0_BITS_PWMB1_CH2 (PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2 << PORTCON_PORTB_SEL0_B0_SHIFT) -#define PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1 4U -#define PORTCON_PORTB_SEL0_B0_BITS_PWMP0_CH1 (PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B0_SHIFT) - -#define PORTCON_PORTB_SEL0_B1_SHIFT 4 -#define PORTCON_PORTB_SEL0_B1_WIDTH 4 -#define PORTCON_PORTB_SEL0_B1_MASK (((1U << PORTCON_PORTB_SEL0_B1_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1 0U -#define PORTCON_PORTB_SEL0_B1_BITS_GPIOB1 (PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1 << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX 1U -#define PORTCON_PORTB_SEL0_B1_BITS_UART2_RX (PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA 2U -#define PORTCON_PORTB_SEL0_B1_BITS_IIC0_SDA (PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA << PORTCON_PORTB_SEL0_B1_SHIFT) -#define PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2 3U -#define PORTCON_PORTB_SEL0_B1_BITS_PWMP0_CH2 (PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL0_B1_SHIFT) - -#define PORTCON_PORTB_SEL0_B2_SHIFT 8 -#define PORTCON_PORTB_SEL0_B2_WIDTH 4 -#define PORTCON_PORTB_SEL0_B2_MASK (((1U << PORTCON_PORTB_SEL0_B2_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2 0U -#define PORTCON_PORTB_SEL0_B2_BITS_GPIOB2 (PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2 << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN 1U -#define PORTCON_PORTB_SEL0_B2_BITS_SPI1_SSN (PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1 2U -#define PORTCON_PORTB_SEL0_B2_BITS_PWMP0_BRAKE1 (PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1 << PORTCON_PORTB_SEL0_B2_SHIFT) -#define PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0 3U -#define PORTCON_PORTB_SEL0_B2_BITS_TIMERP1_HALL0 (PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0 << PORTCON_PORTB_SEL0_B2_SHIFT) - -#define PORTCON_PORTB_SEL0_B3_SHIFT 12 -#define PORTCON_PORTB_SEL0_B3_WIDTH 4 -#define PORTCON_PORTB_SEL0_B3_MASK (((1U << PORTCON_PORTB_SEL0_B3_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3 0U -#define PORTCON_PORTB_SEL0_B3_BITS_GPIOB3 (PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3 << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK 1U -#define PORTCON_PORTB_SEL0_B3_BITS_SPI1_CLK (PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA 2U -#define PORTCON_PORTB_SEL0_B3_BITS_IIC1_SDA (PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N 3U -#define PORTCON_PORTB_SEL0_B3_BITS_PWMP0_CH0N (PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N << PORTCON_PORTB_SEL0_B3_SHIFT) -#define PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1 4U -#define PORTCON_PORTB_SEL0_B3_BITS_TIMERP1_HALL1 (PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1 << PORTCON_PORTB_SEL0_B3_SHIFT) - -#define PORTCON_PORTB_SEL0_B4_SHIFT 16 -#define PORTCON_PORTB_SEL0_B4_WIDTH 4 -#define PORTCON_PORTB_SEL0_B4_MASK (((1U << PORTCON_PORTB_SEL0_B4_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4 0U -#define PORTCON_PORTB_SEL0_B4_BITS_GPIOB4 (PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4 << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO 1U -#define PORTCON_PORTB_SEL0_B4_BITS_SPI1_MISO (PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL 2U -#define PORTCON_PORTB_SEL0_B4_BITS_IIC1_SCL (PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0 3U -#define PORTCON_PORTB_SEL0_B4_BITS_PWMP1_CH0 (PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N 4U -#define PORTCON_PORTB_SEL0_B4_BITS_PWMP0_CH1N (PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N << PORTCON_PORTB_SEL0_B4_SHIFT) -#define PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2 5U -#define PORTCON_PORTB_SEL0_B4_BITS_TIMERP1_HALL2 (PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2 << PORTCON_PORTB_SEL0_B4_SHIFT) - -#define PORTCON_PORTB_SEL0_B5_SHIFT 20 -#define PORTCON_PORTB_SEL0_B5_WIDTH 4 -#define PORTCON_PORTB_SEL0_B5_MASK (((1U << PORTCON_PORTB_SEL0_B5_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5 0U -#define PORTCON_PORTB_SEL0_B5_BITS_GPIOB5 (PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5 << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI 1U -#define PORTCON_PORTB_SEL0_B5_BITS_SPI1_MOSI (PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N 2U -#define PORTCON_PORTB_SEL0_B5_BITS_PWMP1_CH0N (PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N 3U -#define PORTCON_PORTB_SEL0_B5_BITS_PWMP0_CH2N (PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0 4U -#define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_IN0 (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0 << PORTCON_PORTB_SEL0_B5_SHIFT) -#define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L 5U -#define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_OUT_L (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L << PORTCON_PORTB_SEL0_B5_SHIFT) - -#define PORTCON_PORTB_SEL0_B6_SHIFT 24 -#define PORTCON_PORTB_SEL0_B6_WIDTH 4 -#define PORTCON_PORTB_SEL0_B6_MASK (((1U << PORTCON_PORTB_SEL0_B6_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6 0U -#define PORTCON_PORTB_SEL0_B6_BITS_GPIOB6 (PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6 << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0 1U -#define PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0 (PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0 << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1 2U -#define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_IN1 (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1 << PORTCON_PORTB_SEL0_B6_SHIFT) -#define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H 3U -#define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_OUT_H (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H << PORTCON_PORTB_SEL0_B6_SHIFT) - -#define PORTCON_PORTB_SEL0_B7_SHIFT 28 -#define PORTCON_PORTB_SEL0_B7_WIDTH 4 -#define PORTCON_PORTB_SEL0_B7_MASK (((1U << PORTCON_PORTB_SEL0_B7_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7 0U -#define PORTCON_PORTB_SEL0_B7_BITS_GPIOB7 (PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7 << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN 1U -#define PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN (PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX 2U -#define PORTCON_PORTB_SEL0_B7_BITS_UART0_TX (PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL 3U -#define PORTCON_PORTB_SEL0_B7_BITS_IIC0_SCL (PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0 4U -#define PORTCON_PORTB_SEL0_B7_BITS_PWMP1_BRAKE0 (PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0 << PORTCON_PORTB_SEL0_B7_SHIFT) -#define PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1 5U -#define PORTCON_PORTB_SEL0_B7_BITS_PWMP0_CH1 (PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B7_SHIFT) - -#define PORTCON_PORTB_SEL1_ADDR (PORTCON_BASE_ADDR + 0x000CU) -#define PORTCON_PORTB_SEL1 (*(volatile uint32_t *)PORTCON_PORTB_SEL1_ADDR) -#define PORTCON_PORTB_SEL1_B8_SHIFT 0 -#define PORTCON_PORTB_SEL1_B8_WIDTH 4 -#define PORTCON_PORTB_SEL1_B8_MASK (((1U << PORTCON_PORTB_SEL1_B8_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8 0U -#define PORTCON_PORTB_SEL1_B8_BITS_GPIOB8 (PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8 << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK 1U -#define PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK (PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX 2U -#define PORTCON_PORTB_SEL1_B8_BITS_UART0_RX (PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA 3U -#define PORTCON_PORTB_SEL1_B8_BITS_IIC0_SDA (PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0 4U -#define PORTCON_PORTB_SEL1_B8_BITS_PWMB0_CH0 (PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0 << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1 5U -#define PORTCON_PORTB_SEL1_B8_BITS_PWMP1_BRAKE1 (PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1 << PORTCON_PORTB_SEL1_B8_SHIFT) -#define PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2 6U -#define PORTCON_PORTB_SEL1_B8_BITS_PWMP0_CH2 (PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL1_B8_SHIFT) - -#define PORTCON_PORTB_SEL1_B9_SHIFT 4 -#define PORTCON_PORTB_SEL1_B9_WIDTH 4 -#define PORTCON_PORTB_SEL1_B9_MASK (((1U << PORTCON_PORTB_SEL1_B9_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9 0U -#define PORTCON_PORTB_SEL1_B9_BITS_GPIOB9 (PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9 << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO 1U -#define PORTCON_PORTB_SEL1_B9_BITS_SPI0_MISO (PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS 2U -#define PORTCON_PORTB_SEL1_B9_BITS_UART0_CTS (PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1 3U -#define PORTCON_PORTB_SEL1_B9_BITS_PWMB0_CH1 (PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1 << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0 4U -#define PORTCON_PORTB_SEL1_B9_BITS_PWMP1_CH0 (PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1 5U -#define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_IN1 (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1 << PORTCON_PORTB_SEL1_B9_SHIFT) -#define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H 6U -#define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_OUT_H (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H << PORTCON_PORTB_SEL1_B9_SHIFT) - -#define PORTCON_PORTB_SEL1_B10_SHIFT 8 -#define PORTCON_PORTB_SEL1_B10_WIDTH 4 -#define PORTCON_PORTB_SEL1_B10_MASK (((1U << PORTCON_PORTB_SEL1_B10_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10 0U -#define PORTCON_PORTB_SEL1_B10_BITS_GPIOB10 (PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10 << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI 1U -#define PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI (PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS 2U -#define PORTCON_PORTB_SEL1_B10_BITS_UART0_RTS (PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2 3U -#define PORTCON_PORTB_SEL1_B10_BITS_PWMB0_CH2 (PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2 << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1 4U -#define PORTCON_PORTB_SEL1_B10_BITS_PWMP1_CH1 (PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1 << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0 5U -#define PORTCON_PORTB_SEL1_B10_BITS_PWMP0_PLUS0 (PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0 << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0 6U -#define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_IN0 (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0 << PORTCON_PORTB_SEL1_B10_SHIFT) -#define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L 7U -#define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_OUT_L (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L << PORTCON_PORTB_SEL1_B10_SHIFT) - -#define PORTCON_PORTB_SEL1_B11_SHIFT 12 -#define PORTCON_PORTB_SEL1_B11_WIDTH 4 -#define PORTCON_PORTB_SEL1_B11_MASK (((1U << PORTCON_PORTB_SEL1_B11_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11 0U -#define PORTCON_PORTB_SEL1_B11_BITS_GPIOB11 (PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11 << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_VALUE_SWDIO 1U -#define PORTCON_PORTB_SEL1_B11_BITS_SWDIO (PORTCON_PORTB_SEL1_B11_VALUE_SWDIO << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2 2U -#define PORTCON_PORTB_SEL1_B11_BITS_PWMP1_CH2 (PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2 << PORTCON_PORTB_SEL1_B11_SHIFT) -#define PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2 3U -#define PORTCON_PORTB_SEL1_B11_BITS_PWMP0_BRAKE2 (PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2 << PORTCON_PORTB_SEL1_B11_SHIFT) - -#define PORTCON_PORTB_SEL1_B12_SHIFT 16 -#define PORTCON_PORTB_SEL1_B12_WIDTH 4 -#define PORTCON_PORTB_SEL1_B12_MASK (((1U << PORTCON_PORTB_SEL1_B12_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12 0U -#define PORTCON_PORTB_SEL1_B12_BITS_GPIOB12 (PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12 << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX 1U -#define PORTCON_PORTB_SEL1_B12_BITS_UART1_TX (PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL 2U -#define PORTCON_PORTB_SEL1_B12_BITS_IIC1_SCL (PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL << PORTCON_PORTB_SEL1_B12_SHIFT) -#define PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N 3U -#define PORTCON_PORTB_SEL1_B12_BITS_PWMP1_CH0N (PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL1_B12_SHIFT) - -#define PORTCON_PORTB_SEL1_B13_SHIFT 20 -#define PORTCON_PORTB_SEL1_B13_WIDTH 4 -#define PORTCON_PORTB_SEL1_B13_MASK (((1U << PORTCON_PORTB_SEL1_B13_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13 0U -#define PORTCON_PORTB_SEL1_B13_BITS_GPIOB13 (PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13 << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX 1U -#define PORTCON_PORTB_SEL1_B13_BITS_UART1_RX (PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA 2U -#define PORTCON_PORTB_SEL1_B13_BITS_IIC1_SDA (PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA << PORTCON_PORTB_SEL1_B13_SHIFT) -#define PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N 3U -#define PORTCON_PORTB_SEL1_B13_BITS_PWMP1_CH1N (PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N << PORTCON_PORTB_SEL1_B13_SHIFT) - -#define PORTCON_PORTB_SEL1_B14_SHIFT 24 -#define PORTCON_PORTB_SEL1_B14_WIDTH 4 -#define PORTCON_PORTB_SEL1_B14_MASK (((1U << PORTCON_PORTB_SEL1_B14_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14 0U -#define PORTCON_PORTB_SEL1_B14_BITS_GPIOB14 (PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14 << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_VALUE_SWCLK 1U -#define PORTCON_PORTB_SEL1_B14_BITS_SWCLK (PORTCON_PORTB_SEL1_B14_VALUE_SWCLK << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX 2U -#define PORTCON_PORTB_SEL1_B14_BITS_UART2_TX (PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX << PORTCON_PORTB_SEL1_B14_SHIFT) -#define PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N 3U -#define PORTCON_PORTB_SEL1_B14_BITS_PWMP1_CH2N (PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N << PORTCON_PORTB_SEL1_B14_SHIFT) - -#define PORTCON_PORTB_SEL1_B15_SHIFT 28 -#define PORTCON_PORTB_SEL1_B15_WIDTH 4 -#define PORTCON_PORTB_SEL1_B15_MASK (((1U << PORTCON_PORTB_SEL1_B15_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B15_SHIFT) -#define PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15 0U -#define PORTCON_PORTB_SEL1_B15_BITS_GPIOB15 (PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15 << PORTCON_PORTB_SEL1_B15_SHIFT) -#define PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN 1U -#define PORTCON_PORTB_SEL1_B15_BITS_SPI1_SSN (PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN << PORTCON_PORTB_SEL1_B15_SHIFT) -#define PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX 2U -#define PORTCON_PORTB_SEL1_B15_BITS_UART2_RX (PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX << PORTCON_PORTB_SEL1_B15_SHIFT) - -#define PORTCON_PORTC_SEL0_ADDR (PORTCON_BASE_ADDR + 0x0010U) -#define PORTCON_PORTC_SEL0 (*(volatile uint32_t *)PORTCON_PORTC_SEL0_ADDR) -#define PORTCON_PORTC_SEL0_C0_SHIFT 0 -#define PORTCON_PORTC_SEL0_C0_WIDTH 4 -#define PORTCON_PORTC_SEL0_C0_MASK (((1U << PORTCON_PORTC_SEL0_C0_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0 0U -#define PORTCON_PORTC_SEL0_C0_BITS_GPIOC0 (PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0 << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK 1U -#define PORTCON_PORTC_SEL0_C0_BITS_SPI1_CLK (PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS 2U -#define PORTCON_PORTC_SEL0_C0_BITS_UART2_CTS (PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS << PORTCON_PORTC_SEL0_C0_SHIFT) -#define PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0 3U -#define PORTCON_PORTC_SEL0_C0_BITS_PWMB1_CH0 (PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0 << PORTCON_PORTC_SEL0_C0_SHIFT) - -#define PORTCON_PORTC_SEL0_C1_SHIFT 4 -#define PORTCON_PORTC_SEL0_C1_WIDTH 4 -#define PORTCON_PORTC_SEL0_C1_MASK (((1U << PORTCON_PORTC_SEL0_C1_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1 0U -#define PORTCON_PORTC_SEL0_C1_BITS_GPIOC1 (PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1 << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO 1U -#define PORTCON_PORTC_SEL0_C1_BITS_SPI1_MISO (PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS 2U -#define PORTCON_PORTC_SEL0_C1_BITS_UART2_RTS (PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1 3U -#define PORTCON_PORTC_SEL0_C1_BITS_PWMB1_CH1 (PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1 << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0 4U -#define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_IN0 (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0 << PORTCON_PORTC_SEL0_C1_SHIFT) -#define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L 5U -#define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_OUT_L (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L << PORTCON_PORTC_SEL0_C1_SHIFT) - -#define PORTCON_PORTC_SEL0_C2_SHIFT 8 -#define PORTCON_PORTC_SEL0_C2_WIDTH 4 -#define PORTCON_PORTC_SEL0_C2_MASK (((1U << PORTCON_PORTC_SEL0_C2_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2 0U -#define PORTCON_PORTC_SEL0_C2_BITS_GPIOC2 (PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2 << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI 1U -#define PORTCON_PORTC_SEL0_C2_BITS_SPI1_MOSI (PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2 2U -#define PORTCON_PORTC_SEL0_C2_BITS_PWMB1_CH2 (PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2 << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2 3U -#define PORTCON_PORTC_SEL0_C2_BITS_PWMP1_BRAKE2 (PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2 << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1 4U -#define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_IN1 (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1 << PORTCON_PORTC_SEL0_C2_SHIFT) -#define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H 5U -#define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_OUT_H (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H << PORTCON_PORTC_SEL0_C2_SHIFT) - -#define PORTCON_PORTC_SEL0_C3_SHIFT 12 -#define PORTCON_PORTC_SEL0_C3_WIDTH 4 -#define PORTCON_PORTC_SEL0_C3_MASK (((1U << PORTCON_PORTC_SEL0_C3_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3 0U -#define PORTCON_PORTC_SEL0_C3_BITS_GPIOC3 (PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3 << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX 1U -#define PORTCON_PORTC_SEL0_C3_BITS_UART0_TX (PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL 2U -#define PORTCON_PORTC_SEL0_C3_BITS_IIC0_SCL (PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N 3U -#define PORTCON_PORTC_SEL0_C3_BITS_PWMP1_CH1N (PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0 4U -#define PORTCON_PORTC_SEL0_C3_BITS_TIMERP0_HALL0 (PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0 << PORTCON_PORTC_SEL0_C3_SHIFT) -#define PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN 5U -#define PORTCON_PORTC_SEL0_C3_BITS_CMP2_VN (PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN << PORTCON_PORTC_SEL0_C3_SHIFT) - -#define PORTCON_PORTC_SEL0_C4_SHIFT 16 -#define PORTCON_PORTC_SEL0_C4_WIDTH 4 -#define PORTCON_PORTC_SEL0_C4_MASK (((1U << PORTCON_PORTC_SEL0_C4_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4 0U -#define PORTCON_PORTC_SEL0_C4_BITS_GPIOC4 (PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4 << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX 1U -#define PORTCON_PORTC_SEL0_C4_BITS_UART0_RX (PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA 2U -#define PORTCON_PORTC_SEL0_C4_BITS_IIC0_SDA (PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N 3U -#define PORTCON_PORTC_SEL0_C4_BITS_PWMP1_CH2N (PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1 4U -#define PORTCON_PORTC_SEL0_C4_BITS_TIMERP0_HALL1 (PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1 << PORTCON_PORTC_SEL0_C4_SHIFT) -#define PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP 5U -#define PORTCON_PORTC_SEL0_C4_BITS_CMP2_VP (PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP << PORTCON_PORTC_SEL0_C4_SHIFT) - -#define PORTCON_PORTC_SEL0_C5_SHIFT 20 -#define PORTCON_PORTC_SEL0_C5_WIDTH 4 -#define PORTCON_PORTC_SEL0_C5_MASK (((1U << PORTCON_PORTC_SEL0_C5_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5 0U -#define PORTCON_PORTC_SEL0_C5_BITS_GPIOC5 (PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5 << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2 1U -#define PORTCON_PORTC_SEL0_C5_BITS_TIMERP0_HALL2 (PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2 << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_VALUE_TM 2U -#define PORTCON_PORTC_SEL0_C5_BITS_TM (PORTCON_PORTC_SEL0_C5_VALUE_TM << PORTCON_PORTC_SEL0_C5_SHIFT) -#define PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP 3U -#define PORTCON_PORTC_SEL0_C5_BITS_OPA1_VP (PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP << PORTCON_PORTC_SEL0_C5_SHIFT) - -#define PORTCON_PORTC_SEL0_C6_SHIFT 24 -#define PORTCON_PORTC_SEL0_C6_WIDTH 4 -#define PORTCON_PORTC_SEL0_C6_MASK (((1U << PORTCON_PORTC_SEL0_C6_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6 0U -#define PORTCON_PORTC_SEL0_C6_BITS_GPIOC6 (PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6 << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL 1U -#define PORTCON_PORTC_SEL0_C6_BITS_IIC1_SCL (PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1 2U -#define PORTCON_PORTC_SEL0_C6_BITS_PWMP1_CH1 (PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1 << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1 3U -#define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_IN1 (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1 << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H 4U -#define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_OUT_H (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H << PORTCON_PORTC_SEL0_C6_SHIFT) -#define PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN 5U -#define PORTCON_PORTC_SEL0_C6_BITS_OPA1_VN (PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN << PORTCON_PORTC_SEL0_C6_SHIFT) - -#define PORTCON_PORTC_SEL0_C7_SHIFT 28 -#define PORTCON_PORTC_SEL0_C7_WIDTH 4 -#define PORTCON_PORTC_SEL0_C7_MASK (((1U << PORTCON_PORTC_SEL0_C7_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7 0U -#define PORTCON_PORTC_SEL0_C7_BITS_GPIOC7 (PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7 << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA 1U -#define PORTCON_PORTC_SEL0_C7_BITS_IIC1_SDA (PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2 2U -#define PORTCON_PORTC_SEL0_C7_BITS_PWMP1_CH2 (PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2 << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0 3U -#define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_IN0 (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0 << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L 4U -#define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_OUT_L (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L << PORTCON_PORTC_SEL0_C7_SHIFT) -#define PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT 5U -#define PORTCON_PORTC_SEL0_C7_BITS_OPA1_OUT (PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT << PORTCON_PORTC_SEL0_C7_SHIFT) - -#define PORTCON_PORTA_IE_ADDR (PORTCON_BASE_ADDR + 0x0100U) -#define PORTCON_PORTA_IE (*(volatile uint32_t *)PORTCON_PORTA_IE_ADDR) -#define PORTCON_PORTA_IE_A0_SHIFT 0 -#define PORTCON_PORTA_IE_A0_WIDTH 1 -#define PORTCON_PORTA_IE_A0_MASK (((1U << PORTCON_PORTA_IE_A0_WIDTH) - 1U) << PORTCON_PORTA_IE_A0_SHIFT) -#define PORTCON_PORTA_IE_A0_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A0_BITS_DISABLE (PORTCON_PORTA_IE_A0_VALUE_DISABLE << PORTCON_PORTA_IE_A0_SHIFT) -#define PORTCON_PORTA_IE_A0_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A0_BITS_ENABLE (PORTCON_PORTA_IE_A0_VALUE_ENABLE << PORTCON_PORTA_IE_A0_SHIFT) - -#define PORTCON_PORTA_IE_A1_SHIFT 1 -#define PORTCON_PORTA_IE_A1_WIDTH 1 -#define PORTCON_PORTA_IE_A1_MASK (((1U << PORTCON_PORTA_IE_A1_WIDTH) - 1U) << PORTCON_PORTA_IE_A1_SHIFT) -#define PORTCON_PORTA_IE_A1_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A1_BITS_DISABLE (PORTCON_PORTA_IE_A1_VALUE_DISABLE << PORTCON_PORTA_IE_A1_SHIFT) -#define PORTCON_PORTA_IE_A1_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A1_BITS_ENABLE (PORTCON_PORTA_IE_A1_VALUE_ENABLE << PORTCON_PORTA_IE_A1_SHIFT) - -#define PORTCON_PORTA_IE_A2_SHIFT 2 -#define PORTCON_PORTA_IE_A2_WIDTH 1 -#define PORTCON_PORTA_IE_A2_MASK (((1U << PORTCON_PORTA_IE_A2_WIDTH) - 1U) << PORTCON_PORTA_IE_A2_SHIFT) -#define PORTCON_PORTA_IE_A2_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A2_BITS_DISABLE (PORTCON_PORTA_IE_A2_VALUE_DISABLE << PORTCON_PORTA_IE_A2_SHIFT) -#define PORTCON_PORTA_IE_A2_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A2_BITS_ENABLE (PORTCON_PORTA_IE_A2_VALUE_ENABLE << PORTCON_PORTA_IE_A2_SHIFT) - -#define PORTCON_PORTA_IE_A3_SHIFT 3 -#define PORTCON_PORTA_IE_A3_WIDTH 1 -#define PORTCON_PORTA_IE_A3_MASK (((1U << PORTCON_PORTA_IE_A3_WIDTH) - 1U) << PORTCON_PORTA_IE_A3_SHIFT) -#define PORTCON_PORTA_IE_A3_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A3_BITS_DISABLE (PORTCON_PORTA_IE_A3_VALUE_DISABLE << PORTCON_PORTA_IE_A3_SHIFT) -#define PORTCON_PORTA_IE_A3_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A3_BITS_ENABLE (PORTCON_PORTA_IE_A3_VALUE_ENABLE << PORTCON_PORTA_IE_A3_SHIFT) - -#define PORTCON_PORTA_IE_A4_SHIFT 4 -#define PORTCON_PORTA_IE_A4_WIDTH 1 -#define PORTCON_PORTA_IE_A4_MASK (((1U << PORTCON_PORTA_IE_A4_WIDTH) - 1U) << PORTCON_PORTA_IE_A4_SHIFT) -#define PORTCON_PORTA_IE_A4_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A4_BITS_DISABLE (PORTCON_PORTA_IE_A4_VALUE_DISABLE << PORTCON_PORTA_IE_A4_SHIFT) -#define PORTCON_PORTA_IE_A4_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A4_BITS_ENABLE (PORTCON_PORTA_IE_A4_VALUE_ENABLE << PORTCON_PORTA_IE_A4_SHIFT) - -#define PORTCON_PORTA_IE_A5_SHIFT 5 -#define PORTCON_PORTA_IE_A5_WIDTH 1 -#define PORTCON_PORTA_IE_A5_MASK (((1U << PORTCON_PORTA_IE_A5_WIDTH) - 1U) << PORTCON_PORTA_IE_A5_SHIFT) -#define PORTCON_PORTA_IE_A5_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A5_BITS_DISABLE (PORTCON_PORTA_IE_A5_VALUE_DISABLE << PORTCON_PORTA_IE_A5_SHIFT) -#define PORTCON_PORTA_IE_A5_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A5_BITS_ENABLE (PORTCON_PORTA_IE_A5_VALUE_ENABLE << PORTCON_PORTA_IE_A5_SHIFT) - -#define PORTCON_PORTA_IE_A6_SHIFT 6 -#define PORTCON_PORTA_IE_A6_WIDTH 1 -#define PORTCON_PORTA_IE_A6_MASK (((1U << PORTCON_PORTA_IE_A6_WIDTH) - 1U) << PORTCON_PORTA_IE_A6_SHIFT) -#define PORTCON_PORTA_IE_A6_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A6_BITS_DISABLE (PORTCON_PORTA_IE_A6_VALUE_DISABLE << PORTCON_PORTA_IE_A6_SHIFT) -#define PORTCON_PORTA_IE_A6_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A6_BITS_ENABLE (PORTCON_PORTA_IE_A6_VALUE_ENABLE << PORTCON_PORTA_IE_A6_SHIFT) - -#define PORTCON_PORTA_IE_A7_SHIFT 7 -#define PORTCON_PORTA_IE_A7_WIDTH 1 -#define PORTCON_PORTA_IE_A7_MASK (((1U << PORTCON_PORTA_IE_A7_WIDTH) - 1U) << PORTCON_PORTA_IE_A7_SHIFT) -#define PORTCON_PORTA_IE_A7_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A7_BITS_DISABLE (PORTCON_PORTA_IE_A7_VALUE_DISABLE << PORTCON_PORTA_IE_A7_SHIFT) -#define PORTCON_PORTA_IE_A7_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A7_BITS_ENABLE (PORTCON_PORTA_IE_A7_VALUE_ENABLE << PORTCON_PORTA_IE_A7_SHIFT) - -#define PORTCON_PORTA_IE_A8_SHIFT 8 -#define PORTCON_PORTA_IE_A8_WIDTH 1 -#define PORTCON_PORTA_IE_A8_MASK (((1U << PORTCON_PORTA_IE_A8_WIDTH) - 1U) << PORTCON_PORTA_IE_A8_SHIFT) -#define PORTCON_PORTA_IE_A8_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A8_BITS_DISABLE (PORTCON_PORTA_IE_A8_VALUE_DISABLE << PORTCON_PORTA_IE_A8_SHIFT) -#define PORTCON_PORTA_IE_A8_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A8_BITS_ENABLE (PORTCON_PORTA_IE_A8_VALUE_ENABLE << PORTCON_PORTA_IE_A8_SHIFT) - -#define PORTCON_PORTA_IE_A9_SHIFT 9 -#define PORTCON_PORTA_IE_A9_WIDTH 1 -#define PORTCON_PORTA_IE_A9_MASK (((1U << PORTCON_PORTA_IE_A9_WIDTH) - 1U) << PORTCON_PORTA_IE_A9_SHIFT) -#define PORTCON_PORTA_IE_A9_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A9_BITS_DISABLE (PORTCON_PORTA_IE_A9_VALUE_DISABLE << PORTCON_PORTA_IE_A9_SHIFT) -#define PORTCON_PORTA_IE_A9_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A9_BITS_ENABLE (PORTCON_PORTA_IE_A9_VALUE_ENABLE << PORTCON_PORTA_IE_A9_SHIFT) - -#define PORTCON_PORTA_IE_A10_SHIFT 10 -#define PORTCON_PORTA_IE_A10_WIDTH 1 -#define PORTCON_PORTA_IE_A10_MASK (((1U << PORTCON_PORTA_IE_A10_WIDTH) - 1U) << PORTCON_PORTA_IE_A10_SHIFT) -#define PORTCON_PORTA_IE_A10_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A10_BITS_DISABLE (PORTCON_PORTA_IE_A10_VALUE_DISABLE << PORTCON_PORTA_IE_A10_SHIFT) -#define PORTCON_PORTA_IE_A10_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A10_BITS_ENABLE (PORTCON_PORTA_IE_A10_VALUE_ENABLE << PORTCON_PORTA_IE_A10_SHIFT) - -#define PORTCON_PORTA_IE_A11_SHIFT 11 -#define PORTCON_PORTA_IE_A11_WIDTH 1 -#define PORTCON_PORTA_IE_A11_MASK (((1U << PORTCON_PORTA_IE_A11_WIDTH) - 1U) << PORTCON_PORTA_IE_A11_SHIFT) -#define PORTCON_PORTA_IE_A11_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A11_BITS_DISABLE (PORTCON_PORTA_IE_A11_VALUE_DISABLE << PORTCON_PORTA_IE_A11_SHIFT) -#define PORTCON_PORTA_IE_A11_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A11_BITS_ENABLE (PORTCON_PORTA_IE_A11_VALUE_ENABLE << PORTCON_PORTA_IE_A11_SHIFT) - -#define PORTCON_PORTA_IE_A12_SHIFT 12 -#define PORTCON_PORTA_IE_A12_WIDTH 1 -#define PORTCON_PORTA_IE_A12_MASK (((1U << PORTCON_PORTA_IE_A12_WIDTH) - 1U) << PORTCON_PORTA_IE_A12_SHIFT) -#define PORTCON_PORTA_IE_A12_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A12_BITS_DISABLE (PORTCON_PORTA_IE_A12_VALUE_DISABLE << PORTCON_PORTA_IE_A12_SHIFT) -#define PORTCON_PORTA_IE_A12_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A12_BITS_ENABLE (PORTCON_PORTA_IE_A12_VALUE_ENABLE << PORTCON_PORTA_IE_A12_SHIFT) - -#define PORTCON_PORTA_IE_A13_SHIFT 13 -#define PORTCON_PORTA_IE_A13_WIDTH 1 -#define PORTCON_PORTA_IE_A13_MASK (((1U << PORTCON_PORTA_IE_A13_WIDTH) - 1U) << PORTCON_PORTA_IE_A13_SHIFT) -#define PORTCON_PORTA_IE_A13_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A13_BITS_DISABLE (PORTCON_PORTA_IE_A13_VALUE_DISABLE << PORTCON_PORTA_IE_A13_SHIFT) -#define PORTCON_PORTA_IE_A13_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A13_BITS_ENABLE (PORTCON_PORTA_IE_A13_VALUE_ENABLE << PORTCON_PORTA_IE_A13_SHIFT) - -#define PORTCON_PORTA_IE_A14_SHIFT 14 -#define PORTCON_PORTA_IE_A14_WIDTH 1 -#define PORTCON_PORTA_IE_A14_MASK (((1U << PORTCON_PORTA_IE_A14_WIDTH) - 1U) << PORTCON_PORTA_IE_A14_SHIFT) -#define PORTCON_PORTA_IE_A14_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A14_BITS_DISABLE (PORTCON_PORTA_IE_A14_VALUE_DISABLE << PORTCON_PORTA_IE_A14_SHIFT) -#define PORTCON_PORTA_IE_A14_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A14_BITS_ENABLE (PORTCON_PORTA_IE_A14_VALUE_ENABLE << PORTCON_PORTA_IE_A14_SHIFT) - -#define PORTCON_PORTA_IE_A15_SHIFT 15 -#define PORTCON_PORTA_IE_A15_WIDTH 1 -#define PORTCON_PORTA_IE_A15_MASK (((1U << PORTCON_PORTA_IE_A15_WIDTH) - 1U) << PORTCON_PORTA_IE_A15_SHIFT) -#define PORTCON_PORTA_IE_A15_VALUE_DISABLE 0U -#define PORTCON_PORTA_IE_A15_BITS_DISABLE (PORTCON_PORTA_IE_A15_VALUE_DISABLE << PORTCON_PORTA_IE_A15_SHIFT) -#define PORTCON_PORTA_IE_A15_VALUE_ENABLE 1U -#define PORTCON_PORTA_IE_A15_BITS_ENABLE (PORTCON_PORTA_IE_A15_VALUE_ENABLE << PORTCON_PORTA_IE_A15_SHIFT) - -#define PORTCON_PORTB_IE_ADDR (PORTCON_BASE_ADDR + 0x0104U) -#define PORTCON_PORTB_IE (*(volatile uint32_t *)PORTCON_PORTB_IE_ADDR) -#define PORTCON_PORTB_IE_B0_SHIFT 0 -#define PORTCON_PORTB_IE_B0_WIDTH 1 -#define PORTCON_PORTB_IE_B0_MASK (((1U << PORTCON_PORTB_IE_B0_WIDTH) - 1U) << PORTCON_PORTB_IE_B0_SHIFT) -#define PORTCON_PORTB_IE_B0_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B0_BITS_DISABLE (PORTCON_PORTB_IE_B0_VALUE_DISABLE << PORTCON_PORTB_IE_B0_SHIFT) -#define PORTCON_PORTB_IE_B0_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B0_BITS_ENABLE (PORTCON_PORTB_IE_B0_VALUE_ENABLE << PORTCON_PORTB_IE_B0_SHIFT) - -#define PORTCON_PORTB_IE_B1_SHIFT 1 -#define PORTCON_PORTB_IE_B1_WIDTH 1 -#define PORTCON_PORTB_IE_B1_MASK (((1U << PORTCON_PORTB_IE_B1_WIDTH) - 1U) << PORTCON_PORTB_IE_B1_SHIFT) -#define PORTCON_PORTB_IE_B1_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B1_BITS_DISABLE (PORTCON_PORTB_IE_B1_VALUE_DISABLE << PORTCON_PORTB_IE_B1_SHIFT) -#define PORTCON_PORTB_IE_B1_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B1_BITS_ENABLE (PORTCON_PORTB_IE_B1_VALUE_ENABLE << PORTCON_PORTB_IE_B1_SHIFT) - -#define PORTCON_PORTB_IE_B2_SHIFT 2 -#define PORTCON_PORTB_IE_B2_WIDTH 1 -#define PORTCON_PORTB_IE_B2_MASK (((1U << PORTCON_PORTB_IE_B2_WIDTH) - 1U) << PORTCON_PORTB_IE_B2_SHIFT) -#define PORTCON_PORTB_IE_B2_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B2_BITS_DISABLE (PORTCON_PORTB_IE_B2_VALUE_DISABLE << PORTCON_PORTB_IE_B2_SHIFT) -#define PORTCON_PORTB_IE_B2_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B2_BITS_ENABLE (PORTCON_PORTB_IE_B2_VALUE_ENABLE << PORTCON_PORTB_IE_B2_SHIFT) - -#define PORTCON_PORTB_IE_B3_SHIFT 3 -#define PORTCON_PORTB_IE_B3_WIDTH 1 -#define PORTCON_PORTB_IE_B3_MASK (((1U << PORTCON_PORTB_IE_B3_WIDTH) - 1U) << PORTCON_PORTB_IE_B3_SHIFT) -#define PORTCON_PORTB_IE_B3_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B3_BITS_DISABLE (PORTCON_PORTB_IE_B3_VALUE_DISABLE << PORTCON_PORTB_IE_B3_SHIFT) -#define PORTCON_PORTB_IE_B3_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B3_BITS_ENABLE (PORTCON_PORTB_IE_B3_VALUE_ENABLE << PORTCON_PORTB_IE_B3_SHIFT) - -#define PORTCON_PORTB_IE_B4_SHIFT 4 -#define PORTCON_PORTB_IE_B4_WIDTH 1 -#define PORTCON_PORTB_IE_B4_MASK (((1U << PORTCON_PORTB_IE_B4_WIDTH) - 1U) << PORTCON_PORTB_IE_B4_SHIFT) -#define PORTCON_PORTB_IE_B4_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B4_BITS_DISABLE (PORTCON_PORTB_IE_B4_VALUE_DISABLE << PORTCON_PORTB_IE_B4_SHIFT) -#define PORTCON_PORTB_IE_B4_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B4_BITS_ENABLE (PORTCON_PORTB_IE_B4_VALUE_ENABLE << PORTCON_PORTB_IE_B4_SHIFT) - -#define PORTCON_PORTB_IE_B5_SHIFT 5 -#define PORTCON_PORTB_IE_B5_WIDTH 1 -#define PORTCON_PORTB_IE_B5_MASK (((1U << PORTCON_PORTB_IE_B5_WIDTH) - 1U) << PORTCON_PORTB_IE_B5_SHIFT) -#define PORTCON_PORTB_IE_B5_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B5_BITS_DISABLE (PORTCON_PORTB_IE_B5_VALUE_DISABLE << PORTCON_PORTB_IE_B5_SHIFT) -#define PORTCON_PORTB_IE_B5_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B5_BITS_ENABLE (PORTCON_PORTB_IE_B5_VALUE_ENABLE << PORTCON_PORTB_IE_B5_SHIFT) - -#define PORTCON_PORTB_IE_B6_SHIFT 6 -#define PORTCON_PORTB_IE_B6_WIDTH 1 -#define PORTCON_PORTB_IE_B6_MASK (((1U << PORTCON_PORTB_IE_B6_WIDTH) - 1U) << PORTCON_PORTB_IE_B6_SHIFT) -#define PORTCON_PORTB_IE_B6_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B6_BITS_DISABLE (PORTCON_PORTB_IE_B6_VALUE_DISABLE << PORTCON_PORTB_IE_B6_SHIFT) -#define PORTCON_PORTB_IE_B6_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B6_BITS_ENABLE (PORTCON_PORTB_IE_B6_VALUE_ENABLE << PORTCON_PORTB_IE_B6_SHIFT) - -#define PORTCON_PORTB_IE_B7_SHIFT 7 -#define PORTCON_PORTB_IE_B7_WIDTH 1 -#define PORTCON_PORTB_IE_B7_MASK (((1U << PORTCON_PORTB_IE_B7_WIDTH) - 1U) << PORTCON_PORTB_IE_B7_SHIFT) -#define PORTCON_PORTB_IE_B7_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B7_BITS_DISABLE (PORTCON_PORTB_IE_B7_VALUE_DISABLE << PORTCON_PORTB_IE_B7_SHIFT) -#define PORTCON_PORTB_IE_B7_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B7_BITS_ENABLE (PORTCON_PORTB_IE_B7_VALUE_ENABLE << PORTCON_PORTB_IE_B7_SHIFT) - -#define PORTCON_PORTB_IE_B8_SHIFT 8 -#define PORTCON_PORTB_IE_B8_WIDTH 1 -#define PORTCON_PORTB_IE_B8_MASK (((1U << PORTCON_PORTB_IE_B8_WIDTH) - 1U) << PORTCON_PORTB_IE_B8_SHIFT) -#define PORTCON_PORTB_IE_B8_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B8_BITS_DISABLE (PORTCON_PORTB_IE_B8_VALUE_DISABLE << PORTCON_PORTB_IE_B8_SHIFT) -#define PORTCON_PORTB_IE_B8_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B8_BITS_ENABLE (PORTCON_PORTB_IE_B8_VALUE_ENABLE << PORTCON_PORTB_IE_B8_SHIFT) - -#define PORTCON_PORTB_IE_B9_SHIFT 9 -#define PORTCON_PORTB_IE_B9_WIDTH 1 -#define PORTCON_PORTB_IE_B9_MASK (((1U << PORTCON_PORTB_IE_B9_WIDTH) - 1U) << PORTCON_PORTB_IE_B9_SHIFT) -#define PORTCON_PORTB_IE_B9_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B9_BITS_DISABLE (PORTCON_PORTB_IE_B9_VALUE_DISABLE << PORTCON_PORTB_IE_B9_SHIFT) -#define PORTCON_PORTB_IE_B9_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B9_BITS_ENABLE (PORTCON_PORTB_IE_B9_VALUE_ENABLE << PORTCON_PORTB_IE_B9_SHIFT) - -#define PORTCON_PORTB_IE_B10_SHIFT 10 -#define PORTCON_PORTB_IE_B10_WIDTH 1 -#define PORTCON_PORTB_IE_B10_MASK (((1U << PORTCON_PORTB_IE_B10_WIDTH) - 1U) << PORTCON_PORTB_IE_B10_SHIFT) -#define PORTCON_PORTB_IE_B10_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B10_BITS_DISABLE (PORTCON_PORTB_IE_B10_VALUE_DISABLE << PORTCON_PORTB_IE_B10_SHIFT) -#define PORTCON_PORTB_IE_B10_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B10_BITS_ENABLE (PORTCON_PORTB_IE_B10_VALUE_ENABLE << PORTCON_PORTB_IE_B10_SHIFT) - -#define PORTCON_PORTB_IE_B11_SHIFT 11 -#define PORTCON_PORTB_IE_B11_WIDTH 1 -#define PORTCON_PORTB_IE_B11_MASK (((1U << PORTCON_PORTB_IE_B11_WIDTH) - 1U) << PORTCON_PORTB_IE_B11_SHIFT) -#define PORTCON_PORTB_IE_B11_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B11_BITS_DISABLE (PORTCON_PORTB_IE_B11_VALUE_DISABLE << PORTCON_PORTB_IE_B11_SHIFT) -#define PORTCON_PORTB_IE_B11_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B11_BITS_ENABLE (PORTCON_PORTB_IE_B11_VALUE_ENABLE << PORTCON_PORTB_IE_B11_SHIFT) - -#define PORTCON_PORTB_IE_B12_SHIFT 12 -#define PORTCON_PORTB_IE_B12_WIDTH 1 -#define PORTCON_PORTB_IE_B12_MASK (((1U << PORTCON_PORTB_IE_B12_WIDTH) - 1U) << PORTCON_PORTB_IE_B12_SHIFT) -#define PORTCON_PORTB_IE_B12_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B12_BITS_DISABLE (PORTCON_PORTB_IE_B12_VALUE_DISABLE << PORTCON_PORTB_IE_B12_SHIFT) -#define PORTCON_PORTB_IE_B12_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B12_BITS_ENABLE (PORTCON_PORTB_IE_B12_VALUE_ENABLE << PORTCON_PORTB_IE_B12_SHIFT) - -#define PORTCON_PORTB_IE_B13_SHIFT 13 -#define PORTCON_PORTB_IE_B13_WIDTH 1 -#define PORTCON_PORTB_IE_B13_MASK (((1U << PORTCON_PORTB_IE_B13_WIDTH) - 1U) << PORTCON_PORTB_IE_B13_SHIFT) -#define PORTCON_PORTB_IE_B13_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B13_BITS_DISABLE (PORTCON_PORTB_IE_B13_VALUE_DISABLE << PORTCON_PORTB_IE_B13_SHIFT) -#define PORTCON_PORTB_IE_B13_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B13_BITS_ENABLE (PORTCON_PORTB_IE_B13_VALUE_ENABLE << PORTCON_PORTB_IE_B13_SHIFT) - -#define PORTCON_PORTB_IE_B14_SHIFT 14 -#define PORTCON_PORTB_IE_B14_WIDTH 1 -#define PORTCON_PORTB_IE_B14_MASK (((1U << PORTCON_PORTB_IE_B14_WIDTH) - 1U) << PORTCON_PORTB_IE_B14_SHIFT) -#define PORTCON_PORTB_IE_B14_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B14_BITS_DISABLE (PORTCON_PORTB_IE_B14_VALUE_DISABLE << PORTCON_PORTB_IE_B14_SHIFT) -#define PORTCON_PORTB_IE_B14_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B14_BITS_ENABLE (PORTCON_PORTB_IE_B14_VALUE_ENABLE << PORTCON_PORTB_IE_B14_SHIFT) - -#define PORTCON_PORTB_IE_B15_SHIFT 15 -#define PORTCON_PORTB_IE_B15_WIDTH 1 -#define PORTCON_PORTB_IE_B15_MASK (((1U << PORTCON_PORTB_IE_B15_WIDTH) - 1U) << PORTCON_PORTB_IE_B15_SHIFT) -#define PORTCON_PORTB_IE_B15_VALUE_DISABLE 0U -#define PORTCON_PORTB_IE_B15_BITS_DISABLE (PORTCON_PORTB_IE_B15_VALUE_DISABLE << PORTCON_PORTB_IE_B15_SHIFT) -#define PORTCON_PORTB_IE_B15_VALUE_ENABLE 1U -#define PORTCON_PORTB_IE_B15_BITS_ENABLE (PORTCON_PORTB_IE_B15_VALUE_ENABLE << PORTCON_PORTB_IE_B15_SHIFT) - -#define PORTCON_PORTC_IE_ADDR (PORTCON_BASE_ADDR + 0x0108U) -#define PORTCON_PORTC_IE (*(volatile uint32_t *)PORTCON_PORTC_IE_ADDR) -#define PORTCON_PORTC_IE_C0_SHIFT 0 -#define PORTCON_PORTC_IE_C0_WIDTH 1 -#define PORTCON_PORTC_IE_C0_MASK (((1U << PORTCON_PORTC_IE_C0_WIDTH) - 1U) << PORTCON_PORTC_IE_C0_SHIFT) -#define PORTCON_PORTC_IE_C0_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C0_BITS_DISABLE (PORTCON_PORTC_IE_C0_VALUE_DISABLE << PORTCON_PORTC_IE_C0_SHIFT) -#define PORTCON_PORTC_IE_C0_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C0_BITS_ENABLE (PORTCON_PORTC_IE_C0_VALUE_ENABLE << PORTCON_PORTC_IE_C0_SHIFT) - -#define PORTCON_PORTC_IE_C1_SHIFT 1 -#define PORTCON_PORTC_IE_C1_WIDTH 1 -#define PORTCON_PORTC_IE_C1_MASK (((1U << PORTCON_PORTC_IE_C1_WIDTH) - 1U) << PORTCON_PORTC_IE_C1_SHIFT) -#define PORTCON_PORTC_IE_C1_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C1_BITS_DISABLE (PORTCON_PORTC_IE_C1_VALUE_DISABLE << PORTCON_PORTC_IE_C1_SHIFT) -#define PORTCON_PORTC_IE_C1_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C1_BITS_ENABLE (PORTCON_PORTC_IE_C1_VALUE_ENABLE << PORTCON_PORTC_IE_C1_SHIFT) - -#define PORTCON_PORTC_IE_C2_SHIFT 2 -#define PORTCON_PORTC_IE_C2_WIDTH 1 -#define PORTCON_PORTC_IE_C2_MASK (((1U << PORTCON_PORTC_IE_C2_WIDTH) - 1U) << PORTCON_PORTC_IE_C2_SHIFT) -#define PORTCON_PORTC_IE_C2_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C2_BITS_DISABLE (PORTCON_PORTC_IE_C2_VALUE_DISABLE << PORTCON_PORTC_IE_C2_SHIFT) -#define PORTCON_PORTC_IE_C2_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C2_BITS_ENABLE (PORTCON_PORTC_IE_C2_VALUE_ENABLE << PORTCON_PORTC_IE_C2_SHIFT) - -#define PORTCON_PORTC_IE_C3_SHIFT 3 -#define PORTCON_PORTC_IE_C3_WIDTH 1 -#define PORTCON_PORTC_IE_C3_MASK (((1U << PORTCON_PORTC_IE_C3_WIDTH) - 1U) << PORTCON_PORTC_IE_C3_SHIFT) -#define PORTCON_PORTC_IE_C3_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C3_BITS_DISABLE (PORTCON_PORTC_IE_C3_VALUE_DISABLE << PORTCON_PORTC_IE_C3_SHIFT) -#define PORTCON_PORTC_IE_C3_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C3_BITS_ENABLE (PORTCON_PORTC_IE_C3_VALUE_ENABLE << PORTCON_PORTC_IE_C3_SHIFT) - -#define PORTCON_PORTC_IE_C4_SHIFT 4 -#define PORTCON_PORTC_IE_C4_WIDTH 1 -#define PORTCON_PORTC_IE_C4_MASK (((1U << PORTCON_PORTC_IE_C4_WIDTH) - 1U) << PORTCON_PORTC_IE_C4_SHIFT) -#define PORTCON_PORTC_IE_C4_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C4_BITS_DISABLE (PORTCON_PORTC_IE_C4_VALUE_DISABLE << PORTCON_PORTC_IE_C4_SHIFT) -#define PORTCON_PORTC_IE_C4_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C4_BITS_ENABLE (PORTCON_PORTC_IE_C4_VALUE_ENABLE << PORTCON_PORTC_IE_C4_SHIFT) - -#define PORTCON_PORTC_IE_C5_SHIFT 5 -#define PORTCON_PORTC_IE_C5_WIDTH 1 -#define PORTCON_PORTC_IE_C5_MASK (((1U << PORTCON_PORTC_IE_C5_WIDTH) - 1U) << PORTCON_PORTC_IE_C5_SHIFT) -#define PORTCON_PORTC_IE_C5_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C5_BITS_DISABLE (PORTCON_PORTC_IE_C5_VALUE_DISABLE << PORTCON_PORTC_IE_C5_SHIFT) -#define PORTCON_PORTC_IE_C5_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C5_BITS_ENABLE (PORTCON_PORTC_IE_C5_VALUE_ENABLE << PORTCON_PORTC_IE_C5_SHIFT) - -#define PORTCON_PORTC_IE_C6_SHIFT 6 -#define PORTCON_PORTC_IE_C6_WIDTH 1 -#define PORTCON_PORTC_IE_C6_MASK (((1U << PORTCON_PORTC_IE_C6_WIDTH) - 1U) << PORTCON_PORTC_IE_C6_SHIFT) -#define PORTCON_PORTC_IE_C6_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C6_BITS_DISABLE (PORTCON_PORTC_IE_C6_VALUE_DISABLE << PORTCON_PORTC_IE_C6_SHIFT) -#define PORTCON_PORTC_IE_C6_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C6_BITS_ENABLE (PORTCON_PORTC_IE_C6_VALUE_ENABLE << PORTCON_PORTC_IE_C6_SHIFT) - -#define PORTCON_PORTC_IE_C7_SHIFT 7 -#define PORTCON_PORTC_IE_C7_WIDTH 1 -#define PORTCON_PORTC_IE_C7_MASK (((1U << PORTCON_PORTC_IE_C7_WIDTH) - 1U) << PORTCON_PORTC_IE_C7_SHIFT) -#define PORTCON_PORTC_IE_C7_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C7_BITS_DISABLE (PORTCON_PORTC_IE_C7_VALUE_DISABLE << PORTCON_PORTC_IE_C7_SHIFT) -#define PORTCON_PORTC_IE_C7_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C7_BITS_ENABLE (PORTCON_PORTC_IE_C7_VALUE_ENABLE << PORTCON_PORTC_IE_C7_SHIFT) - -#define PORTCON_PORTC_IE_C8_SHIFT 8 -#define PORTCON_PORTC_IE_C8_WIDTH 1 -#define PORTCON_PORTC_IE_C8_MASK (((1U << PORTCON_PORTC_IE_C8_WIDTH) - 1U) << PORTCON_PORTC_IE_C8_SHIFT) -#define PORTCON_PORTC_IE_C8_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C8_BITS_DISABLE (PORTCON_PORTC_IE_C8_VALUE_DISABLE << PORTCON_PORTC_IE_C8_SHIFT) -#define PORTCON_PORTC_IE_C8_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C8_BITS_ENABLE (PORTCON_PORTC_IE_C8_VALUE_ENABLE << PORTCON_PORTC_IE_C8_SHIFT) - -#define PORTCON_PORTC_IE_C9_SHIFT 9 -#define PORTCON_PORTC_IE_C9_WIDTH 1 -#define PORTCON_PORTC_IE_C9_MASK (((1U << PORTCON_PORTC_IE_C9_WIDTH) - 1U) << PORTCON_PORTC_IE_C9_SHIFT) -#define PORTCON_PORTC_IE_C9_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C9_BITS_DISABLE (PORTCON_PORTC_IE_C9_VALUE_DISABLE << PORTCON_PORTC_IE_C9_SHIFT) -#define PORTCON_PORTC_IE_C9_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C9_BITS_ENABLE (PORTCON_PORTC_IE_C9_VALUE_ENABLE << PORTCON_PORTC_IE_C9_SHIFT) - -#define PORTCON_PORTC_IE_C10_SHIFT 10 -#define PORTCON_PORTC_IE_C10_WIDTH 1 -#define PORTCON_PORTC_IE_C10_MASK (((1U << PORTCON_PORTC_IE_C10_WIDTH) - 1U) << PORTCON_PORTC_IE_C10_SHIFT) -#define PORTCON_PORTC_IE_C10_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C10_BITS_DISABLE (PORTCON_PORTC_IE_C10_VALUE_DISABLE << PORTCON_PORTC_IE_C10_SHIFT) -#define PORTCON_PORTC_IE_C10_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C10_BITS_ENABLE (PORTCON_PORTC_IE_C10_VALUE_ENABLE << PORTCON_PORTC_IE_C10_SHIFT) - -#define PORTCON_PORTC_IE_C11_SHIFT 11 -#define PORTCON_PORTC_IE_C11_WIDTH 1 -#define PORTCON_PORTC_IE_C11_MASK (((1U << PORTCON_PORTC_IE_C11_WIDTH) - 1U) << PORTCON_PORTC_IE_C11_SHIFT) -#define PORTCON_PORTC_IE_C11_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C11_BITS_DISABLE (PORTCON_PORTC_IE_C11_VALUE_DISABLE << PORTCON_PORTC_IE_C11_SHIFT) -#define PORTCON_PORTC_IE_C11_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C11_BITS_ENABLE (PORTCON_PORTC_IE_C11_VALUE_ENABLE << PORTCON_PORTC_IE_C11_SHIFT) - -#define PORTCON_PORTC_IE_C12_SHIFT 12 -#define PORTCON_PORTC_IE_C12_WIDTH 1 -#define PORTCON_PORTC_IE_C12_MASK (((1U << PORTCON_PORTC_IE_C12_WIDTH) - 1U) << PORTCON_PORTC_IE_C12_SHIFT) -#define PORTCON_PORTC_IE_C12_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C12_BITS_DISABLE (PORTCON_PORTC_IE_C12_VALUE_DISABLE << PORTCON_PORTC_IE_C12_SHIFT) -#define PORTCON_PORTC_IE_C12_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C12_BITS_ENABLE (PORTCON_PORTC_IE_C12_VALUE_ENABLE << PORTCON_PORTC_IE_C12_SHIFT) - -#define PORTCON_PORTC_IE_C13_SHIFT 13 -#define PORTCON_PORTC_IE_C13_WIDTH 1 -#define PORTCON_PORTC_IE_C13_MASK (((1U << PORTCON_PORTC_IE_C13_WIDTH) - 1U) << PORTCON_PORTC_IE_C13_SHIFT) -#define PORTCON_PORTC_IE_C13_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C13_BITS_DISABLE (PORTCON_PORTC_IE_C13_VALUE_DISABLE << PORTCON_PORTC_IE_C13_SHIFT) -#define PORTCON_PORTC_IE_C13_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C13_BITS_ENABLE (PORTCON_PORTC_IE_C13_VALUE_ENABLE << PORTCON_PORTC_IE_C13_SHIFT) - -#define PORTCON_PORTC_IE_C14_SHIFT 14 -#define PORTCON_PORTC_IE_C14_WIDTH 1 -#define PORTCON_PORTC_IE_C14_MASK (((1U << PORTCON_PORTC_IE_C14_WIDTH) - 1U) << PORTCON_PORTC_IE_C14_SHIFT) -#define PORTCON_PORTC_IE_C14_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C14_BITS_DISABLE (PORTCON_PORTC_IE_C14_VALUE_DISABLE << PORTCON_PORTC_IE_C14_SHIFT) -#define PORTCON_PORTC_IE_C14_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C14_BITS_ENABLE (PORTCON_PORTC_IE_C14_VALUE_ENABLE << PORTCON_PORTC_IE_C14_SHIFT) - -#define PORTCON_PORTC_IE_C15_SHIFT 15 -#define PORTCON_PORTC_IE_C15_WIDTH 1 -#define PORTCON_PORTC_IE_C15_MASK (((1U << PORTCON_PORTC_IE_C15_WIDTH) - 1U) << PORTCON_PORTC_IE_C15_SHIFT) -#define PORTCON_PORTC_IE_C15_VALUE_DISABLE 0U -#define PORTCON_PORTC_IE_C15_BITS_DISABLE (PORTCON_PORTC_IE_C15_VALUE_DISABLE << PORTCON_PORTC_IE_C15_SHIFT) -#define PORTCON_PORTC_IE_C15_VALUE_ENABLE 1U -#define PORTCON_PORTC_IE_C15_BITS_ENABLE (PORTCON_PORTC_IE_C15_VALUE_ENABLE << PORTCON_PORTC_IE_C15_SHIFT) - -#define PORTCON_PORTA_PU_ADDR (PORTCON_BASE_ADDR + 0x0200U) -#define PORTCON_PORTA_PU (*(volatile uint32_t *)PORTCON_PORTA_PU_ADDR) -#define PORTCON_PORTA_PU_A0_SHIFT 0 -#define PORTCON_PORTA_PU_A0_WIDTH 1 -#define PORTCON_PORTA_PU_A0_MASK (((1U << PORTCON_PORTA_PU_A0_WIDTH) - 1U) << PORTCON_PORTA_PU_A0_SHIFT) -#define PORTCON_PORTA_PU_A0_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A0_BITS_DISABLE (PORTCON_PORTA_PU_A0_VALUE_DISABLE << PORTCON_PORTA_PU_A0_SHIFT) -#define PORTCON_PORTA_PU_A0_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A0_BITS_ENABLE (PORTCON_PORTA_PU_A0_VALUE_ENABLE << PORTCON_PORTA_PU_A0_SHIFT) - -#define PORTCON_PORTA_PU_A1_SHIFT 1 -#define PORTCON_PORTA_PU_A1_WIDTH 1 -#define PORTCON_PORTA_PU_A1_MASK (((1U << PORTCON_PORTA_PU_A1_WIDTH) - 1U) << PORTCON_PORTA_PU_A1_SHIFT) -#define PORTCON_PORTA_PU_A1_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A1_BITS_DISABLE (PORTCON_PORTA_PU_A1_VALUE_DISABLE << PORTCON_PORTA_PU_A1_SHIFT) -#define PORTCON_PORTA_PU_A1_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A1_BITS_ENABLE (PORTCON_PORTA_PU_A1_VALUE_ENABLE << PORTCON_PORTA_PU_A1_SHIFT) - -#define PORTCON_PORTA_PU_A2_SHIFT 2 -#define PORTCON_PORTA_PU_A2_WIDTH 1 -#define PORTCON_PORTA_PU_A2_MASK (((1U << PORTCON_PORTA_PU_A2_WIDTH) - 1U) << PORTCON_PORTA_PU_A2_SHIFT) -#define PORTCON_PORTA_PU_A2_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A2_BITS_DISABLE (PORTCON_PORTA_PU_A2_VALUE_DISABLE << PORTCON_PORTA_PU_A2_SHIFT) -#define PORTCON_PORTA_PU_A2_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A2_BITS_ENABLE (PORTCON_PORTA_PU_A2_VALUE_ENABLE << PORTCON_PORTA_PU_A2_SHIFT) - -#define PORTCON_PORTA_PU_A3_SHIFT 3 -#define PORTCON_PORTA_PU_A3_WIDTH 1 -#define PORTCON_PORTA_PU_A3_MASK (((1U << PORTCON_PORTA_PU_A3_WIDTH) - 1U) << PORTCON_PORTA_PU_A3_SHIFT) -#define PORTCON_PORTA_PU_A3_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A3_BITS_DISABLE (PORTCON_PORTA_PU_A3_VALUE_DISABLE << PORTCON_PORTA_PU_A3_SHIFT) -#define PORTCON_PORTA_PU_A3_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A3_BITS_ENABLE (PORTCON_PORTA_PU_A3_VALUE_ENABLE << PORTCON_PORTA_PU_A3_SHIFT) - -#define PORTCON_PORTA_PU_A4_SHIFT 4 -#define PORTCON_PORTA_PU_A4_WIDTH 1 -#define PORTCON_PORTA_PU_A4_MASK (((1U << PORTCON_PORTA_PU_A4_WIDTH) - 1U) << PORTCON_PORTA_PU_A4_SHIFT) -#define PORTCON_PORTA_PU_A4_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A4_BITS_DISABLE (PORTCON_PORTA_PU_A4_VALUE_DISABLE << PORTCON_PORTA_PU_A4_SHIFT) -#define PORTCON_PORTA_PU_A4_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A4_BITS_ENABLE (PORTCON_PORTA_PU_A4_VALUE_ENABLE << PORTCON_PORTA_PU_A4_SHIFT) - -#define PORTCON_PORTA_PU_A5_SHIFT 5 -#define PORTCON_PORTA_PU_A5_WIDTH 1 -#define PORTCON_PORTA_PU_A5_MASK (((1U << PORTCON_PORTA_PU_A5_WIDTH) - 1U) << PORTCON_PORTA_PU_A5_SHIFT) -#define PORTCON_PORTA_PU_A5_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A5_BITS_DISABLE (PORTCON_PORTA_PU_A5_VALUE_DISABLE << PORTCON_PORTA_PU_A5_SHIFT) -#define PORTCON_PORTA_PU_A5_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A5_BITS_ENABLE (PORTCON_PORTA_PU_A5_VALUE_ENABLE << PORTCON_PORTA_PU_A5_SHIFT) - -#define PORTCON_PORTA_PU_A6_SHIFT 6 -#define PORTCON_PORTA_PU_A6_WIDTH 1 -#define PORTCON_PORTA_PU_A6_MASK (((1U << PORTCON_PORTA_PU_A6_WIDTH) - 1U) << PORTCON_PORTA_PU_A6_SHIFT) -#define PORTCON_PORTA_PU_A6_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A6_BITS_DISABLE (PORTCON_PORTA_PU_A6_VALUE_DISABLE << PORTCON_PORTA_PU_A6_SHIFT) -#define PORTCON_PORTA_PU_A6_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A6_BITS_ENABLE (PORTCON_PORTA_PU_A6_VALUE_ENABLE << PORTCON_PORTA_PU_A6_SHIFT) - -#define PORTCON_PORTA_PU_A7_SHIFT 7 -#define PORTCON_PORTA_PU_A7_WIDTH 1 -#define PORTCON_PORTA_PU_A7_MASK (((1U << PORTCON_PORTA_PU_A7_WIDTH) - 1U) << PORTCON_PORTA_PU_A7_SHIFT) -#define PORTCON_PORTA_PU_A7_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A7_BITS_DISABLE (PORTCON_PORTA_PU_A7_VALUE_DISABLE << PORTCON_PORTA_PU_A7_SHIFT) -#define PORTCON_PORTA_PU_A7_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A7_BITS_ENABLE (PORTCON_PORTA_PU_A7_VALUE_ENABLE << PORTCON_PORTA_PU_A7_SHIFT) - -#define PORTCON_PORTA_PU_A8_SHIFT 8 -#define PORTCON_PORTA_PU_A8_WIDTH 1 -#define PORTCON_PORTA_PU_A8_MASK (((1U << PORTCON_PORTA_PU_A8_WIDTH) - 1U) << PORTCON_PORTA_PU_A8_SHIFT) -#define PORTCON_PORTA_PU_A8_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A8_BITS_DISABLE (PORTCON_PORTA_PU_A8_VALUE_DISABLE << PORTCON_PORTA_PU_A8_SHIFT) -#define PORTCON_PORTA_PU_A8_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A8_BITS_ENABLE (PORTCON_PORTA_PU_A8_VALUE_ENABLE << PORTCON_PORTA_PU_A8_SHIFT) - -#define PORTCON_PORTA_PU_A9_SHIFT 9 -#define PORTCON_PORTA_PU_A9_WIDTH 1 -#define PORTCON_PORTA_PU_A9_MASK (((1U << PORTCON_PORTA_PU_A9_WIDTH) - 1U) << PORTCON_PORTA_PU_A9_SHIFT) -#define PORTCON_PORTA_PU_A9_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A9_BITS_DISABLE (PORTCON_PORTA_PU_A9_VALUE_DISABLE << PORTCON_PORTA_PU_A9_SHIFT) -#define PORTCON_PORTA_PU_A9_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A9_BITS_ENABLE (PORTCON_PORTA_PU_A9_VALUE_ENABLE << PORTCON_PORTA_PU_A9_SHIFT) - -#define PORTCON_PORTA_PU_A10_SHIFT 10 -#define PORTCON_PORTA_PU_A10_WIDTH 1 -#define PORTCON_PORTA_PU_A10_MASK (((1U << PORTCON_PORTA_PU_A10_WIDTH) - 1U) << PORTCON_PORTA_PU_A10_SHIFT) -#define PORTCON_PORTA_PU_A10_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A10_BITS_DISABLE (PORTCON_PORTA_PU_A10_VALUE_DISABLE << PORTCON_PORTA_PU_A10_SHIFT) -#define PORTCON_PORTA_PU_A10_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A10_BITS_ENABLE (PORTCON_PORTA_PU_A10_VALUE_ENABLE << PORTCON_PORTA_PU_A10_SHIFT) - -#define PORTCON_PORTA_PU_A11_SHIFT 11 -#define PORTCON_PORTA_PU_A11_WIDTH 1 -#define PORTCON_PORTA_PU_A11_MASK (((1U << PORTCON_PORTA_PU_A11_WIDTH) - 1U) << PORTCON_PORTA_PU_A11_SHIFT) -#define PORTCON_PORTA_PU_A11_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A11_BITS_DISABLE (PORTCON_PORTA_PU_A11_VALUE_DISABLE << PORTCON_PORTA_PU_A11_SHIFT) -#define PORTCON_PORTA_PU_A11_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A11_BITS_ENABLE (PORTCON_PORTA_PU_A11_VALUE_ENABLE << PORTCON_PORTA_PU_A11_SHIFT) - -#define PORTCON_PORTA_PU_A12_SHIFT 12 -#define PORTCON_PORTA_PU_A12_WIDTH 1 -#define PORTCON_PORTA_PU_A12_MASK (((1U << PORTCON_PORTA_PU_A12_WIDTH) - 1U) << PORTCON_PORTA_PU_A12_SHIFT) -#define PORTCON_PORTA_PU_A12_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A12_BITS_DISABLE (PORTCON_PORTA_PU_A12_VALUE_DISABLE << PORTCON_PORTA_PU_A12_SHIFT) -#define PORTCON_PORTA_PU_A12_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A12_BITS_ENABLE (PORTCON_PORTA_PU_A12_VALUE_ENABLE << PORTCON_PORTA_PU_A12_SHIFT) - -#define PORTCON_PORTA_PU_A13_SHIFT 13 -#define PORTCON_PORTA_PU_A13_WIDTH 1 -#define PORTCON_PORTA_PU_A13_MASK (((1U << PORTCON_PORTA_PU_A13_WIDTH) - 1U) << PORTCON_PORTA_PU_A13_SHIFT) -#define PORTCON_PORTA_PU_A13_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A13_BITS_DISABLE (PORTCON_PORTA_PU_A13_VALUE_DISABLE << PORTCON_PORTA_PU_A13_SHIFT) -#define PORTCON_PORTA_PU_A13_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A13_BITS_ENABLE (PORTCON_PORTA_PU_A13_VALUE_ENABLE << PORTCON_PORTA_PU_A13_SHIFT) - -#define PORTCON_PORTA_PU_A14_SHIFT 14 -#define PORTCON_PORTA_PU_A14_WIDTH 1 -#define PORTCON_PORTA_PU_A14_MASK (((1U << PORTCON_PORTA_PU_A14_WIDTH) - 1U) << PORTCON_PORTA_PU_A14_SHIFT) -#define PORTCON_PORTA_PU_A14_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A14_BITS_DISABLE (PORTCON_PORTA_PU_A14_VALUE_DISABLE << PORTCON_PORTA_PU_A14_SHIFT) -#define PORTCON_PORTA_PU_A14_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A14_BITS_ENABLE (PORTCON_PORTA_PU_A14_VALUE_ENABLE << PORTCON_PORTA_PU_A14_SHIFT) - -#define PORTCON_PORTA_PU_A15_SHIFT 15 -#define PORTCON_PORTA_PU_A15_WIDTH 1 -#define PORTCON_PORTA_PU_A15_MASK (((1U << PORTCON_PORTA_PU_A15_WIDTH) - 1U) << PORTCON_PORTA_PU_A15_SHIFT) -#define PORTCON_PORTA_PU_A15_VALUE_DISABLE 0U -#define PORTCON_PORTA_PU_A15_BITS_DISABLE (PORTCON_PORTA_PU_A15_VALUE_DISABLE << PORTCON_PORTA_PU_A15_SHIFT) -#define PORTCON_PORTA_PU_A15_VALUE_ENABLE 1U -#define PORTCON_PORTA_PU_A15_BITS_ENABLE (PORTCON_PORTA_PU_A15_VALUE_ENABLE << PORTCON_PORTA_PU_A15_SHIFT) - -#define PORTCON_PORTB_PU_ADDR (PORTCON_BASE_ADDR + 0x0204U) -#define PORTCON_PORTB_PU (*(volatile uint32_t *)PORTCON_PORTB_PU_ADDR) -#define PORTCON_PORTB_PU_B0_SHIFT 0 -#define PORTCON_PORTB_PU_B0_WIDTH 1 -#define PORTCON_PORTB_PU_B0_MASK (((1U << PORTCON_PORTB_PU_B0_WIDTH) - 1U) << PORTCON_PORTB_PU_B0_SHIFT) -#define PORTCON_PORTB_PU_B0_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B0_BITS_DISABLE (PORTCON_PORTB_PU_B0_VALUE_DISABLE << PORTCON_PORTB_PU_B0_SHIFT) -#define PORTCON_PORTB_PU_B0_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B0_BITS_ENABLE (PORTCON_PORTB_PU_B0_VALUE_ENABLE << PORTCON_PORTB_PU_B0_SHIFT) - -#define PORTCON_PORTB_PU_B1_SHIFT 1 -#define PORTCON_PORTB_PU_B1_WIDTH 1 -#define PORTCON_PORTB_PU_B1_MASK (((1U << PORTCON_PORTB_PU_B1_WIDTH) - 1U) << PORTCON_PORTB_PU_B1_SHIFT) -#define PORTCON_PORTB_PU_B1_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B1_BITS_DISABLE (PORTCON_PORTB_PU_B1_VALUE_DISABLE << PORTCON_PORTB_PU_B1_SHIFT) -#define PORTCON_PORTB_PU_B1_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B1_BITS_ENABLE (PORTCON_PORTB_PU_B1_VALUE_ENABLE << PORTCON_PORTB_PU_B1_SHIFT) - -#define PORTCON_PORTB_PU_B2_SHIFT 2 -#define PORTCON_PORTB_PU_B2_WIDTH 1 -#define PORTCON_PORTB_PU_B2_MASK (((1U << PORTCON_PORTB_PU_B2_WIDTH) - 1U) << PORTCON_PORTB_PU_B2_SHIFT) -#define PORTCON_PORTB_PU_B2_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B2_BITS_DISABLE (PORTCON_PORTB_PU_B2_VALUE_DISABLE << PORTCON_PORTB_PU_B2_SHIFT) -#define PORTCON_PORTB_PU_B2_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B2_BITS_ENABLE (PORTCON_PORTB_PU_B2_VALUE_ENABLE << PORTCON_PORTB_PU_B2_SHIFT) - -#define PORTCON_PORTB_PU_B3_SHIFT 3 -#define PORTCON_PORTB_PU_B3_WIDTH 1 -#define PORTCON_PORTB_PU_B3_MASK (((1U << PORTCON_PORTB_PU_B3_WIDTH) - 1U) << PORTCON_PORTB_PU_B3_SHIFT) -#define PORTCON_PORTB_PU_B3_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B3_BITS_DISABLE (PORTCON_PORTB_PU_B3_VALUE_DISABLE << PORTCON_PORTB_PU_B3_SHIFT) -#define PORTCON_PORTB_PU_B3_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B3_BITS_ENABLE (PORTCON_PORTB_PU_B3_VALUE_ENABLE << PORTCON_PORTB_PU_B3_SHIFT) - -#define PORTCON_PORTB_PU_B4_SHIFT 4 -#define PORTCON_PORTB_PU_B4_WIDTH 1 -#define PORTCON_PORTB_PU_B4_MASK (((1U << PORTCON_PORTB_PU_B4_WIDTH) - 1U) << PORTCON_PORTB_PU_B4_SHIFT) -#define PORTCON_PORTB_PU_B4_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B4_BITS_DISABLE (PORTCON_PORTB_PU_B4_VALUE_DISABLE << PORTCON_PORTB_PU_B4_SHIFT) -#define PORTCON_PORTB_PU_B4_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B4_BITS_ENABLE (PORTCON_PORTB_PU_B4_VALUE_ENABLE << PORTCON_PORTB_PU_B4_SHIFT) - -#define PORTCON_PORTB_PU_B5_SHIFT 5 -#define PORTCON_PORTB_PU_B5_WIDTH 1 -#define PORTCON_PORTB_PU_B5_MASK (((1U << PORTCON_PORTB_PU_B5_WIDTH) - 1U) << PORTCON_PORTB_PU_B5_SHIFT) -#define PORTCON_PORTB_PU_B5_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B5_BITS_DISABLE (PORTCON_PORTB_PU_B5_VALUE_DISABLE << PORTCON_PORTB_PU_B5_SHIFT) -#define PORTCON_PORTB_PU_B5_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B5_BITS_ENABLE (PORTCON_PORTB_PU_B5_VALUE_ENABLE << PORTCON_PORTB_PU_B5_SHIFT) - -#define PORTCON_PORTB_PU_B6_SHIFT 6 -#define PORTCON_PORTB_PU_B6_WIDTH 1 -#define PORTCON_PORTB_PU_B6_MASK (((1U << PORTCON_PORTB_PU_B6_WIDTH) - 1U) << PORTCON_PORTB_PU_B6_SHIFT) -#define PORTCON_PORTB_PU_B6_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B6_BITS_DISABLE (PORTCON_PORTB_PU_B6_VALUE_DISABLE << PORTCON_PORTB_PU_B6_SHIFT) -#define PORTCON_PORTB_PU_B6_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B6_BITS_ENABLE (PORTCON_PORTB_PU_B6_VALUE_ENABLE << PORTCON_PORTB_PU_B6_SHIFT) - -#define PORTCON_PORTB_PU_B7_SHIFT 7 -#define PORTCON_PORTB_PU_B7_WIDTH 1 -#define PORTCON_PORTB_PU_B7_MASK (((1U << PORTCON_PORTB_PU_B7_WIDTH) - 1U) << PORTCON_PORTB_PU_B7_SHIFT) -#define PORTCON_PORTB_PU_B7_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B7_BITS_DISABLE (PORTCON_PORTB_PU_B7_VALUE_DISABLE << PORTCON_PORTB_PU_B7_SHIFT) -#define PORTCON_PORTB_PU_B7_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B7_BITS_ENABLE (PORTCON_PORTB_PU_B7_VALUE_ENABLE << PORTCON_PORTB_PU_B7_SHIFT) - -#define PORTCON_PORTB_PU_B8_SHIFT 8 -#define PORTCON_PORTB_PU_B8_WIDTH 1 -#define PORTCON_PORTB_PU_B8_MASK (((1U << PORTCON_PORTB_PU_B8_WIDTH) - 1U) << PORTCON_PORTB_PU_B8_SHIFT) -#define PORTCON_PORTB_PU_B8_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B8_BITS_DISABLE (PORTCON_PORTB_PU_B8_VALUE_DISABLE << PORTCON_PORTB_PU_B8_SHIFT) -#define PORTCON_PORTB_PU_B8_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B8_BITS_ENABLE (PORTCON_PORTB_PU_B8_VALUE_ENABLE << PORTCON_PORTB_PU_B8_SHIFT) - -#define PORTCON_PORTB_PU_B9_SHIFT 9 -#define PORTCON_PORTB_PU_B9_WIDTH 1 -#define PORTCON_PORTB_PU_B9_MASK (((1U << PORTCON_PORTB_PU_B9_WIDTH) - 1U) << PORTCON_PORTB_PU_B9_SHIFT) -#define PORTCON_PORTB_PU_B9_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B9_BITS_DISABLE (PORTCON_PORTB_PU_B9_VALUE_DISABLE << PORTCON_PORTB_PU_B9_SHIFT) -#define PORTCON_PORTB_PU_B9_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B9_BITS_ENABLE (PORTCON_PORTB_PU_B9_VALUE_ENABLE << PORTCON_PORTB_PU_B9_SHIFT) - -#define PORTCON_PORTB_PU_B10_SHIFT 10 -#define PORTCON_PORTB_PU_B10_WIDTH 1 -#define PORTCON_PORTB_PU_B10_MASK (((1U << PORTCON_PORTB_PU_B10_WIDTH) - 1U) << PORTCON_PORTB_PU_B10_SHIFT) -#define PORTCON_PORTB_PU_B10_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B10_BITS_DISABLE (PORTCON_PORTB_PU_B10_VALUE_DISABLE << PORTCON_PORTB_PU_B10_SHIFT) -#define PORTCON_PORTB_PU_B10_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B10_BITS_ENABLE (PORTCON_PORTB_PU_B10_VALUE_ENABLE << PORTCON_PORTB_PU_B10_SHIFT) - -#define PORTCON_PORTB_PU_B11_SHIFT 11 -#define PORTCON_PORTB_PU_B11_WIDTH 1 -#define PORTCON_PORTB_PU_B11_MASK (((1U << PORTCON_PORTB_PU_B11_WIDTH) - 1U) << PORTCON_PORTB_PU_B11_SHIFT) -#define PORTCON_PORTB_PU_B11_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B11_BITS_DISABLE (PORTCON_PORTB_PU_B11_VALUE_DISABLE << PORTCON_PORTB_PU_B11_SHIFT) -#define PORTCON_PORTB_PU_B11_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B11_BITS_ENABLE (PORTCON_PORTB_PU_B11_VALUE_ENABLE << PORTCON_PORTB_PU_B11_SHIFT) - -#define PORTCON_PORTB_PU_B12_SHIFT 12 -#define PORTCON_PORTB_PU_B12_WIDTH 1 -#define PORTCON_PORTB_PU_B12_MASK (((1U << PORTCON_PORTB_PU_B12_WIDTH) - 1U) << PORTCON_PORTB_PU_B12_SHIFT) -#define PORTCON_PORTB_PU_B12_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B12_BITS_DISABLE (PORTCON_PORTB_PU_B12_VALUE_DISABLE << PORTCON_PORTB_PU_B12_SHIFT) -#define PORTCON_PORTB_PU_B12_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B12_BITS_ENABLE (PORTCON_PORTB_PU_B12_VALUE_ENABLE << PORTCON_PORTB_PU_B12_SHIFT) - -#define PORTCON_PORTB_PU_B13_SHIFT 13 -#define PORTCON_PORTB_PU_B13_WIDTH 1 -#define PORTCON_PORTB_PU_B13_MASK (((1U << PORTCON_PORTB_PU_B13_WIDTH) - 1U) << PORTCON_PORTB_PU_B13_SHIFT) -#define PORTCON_PORTB_PU_B13_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B13_BITS_DISABLE (PORTCON_PORTB_PU_B13_VALUE_DISABLE << PORTCON_PORTB_PU_B13_SHIFT) -#define PORTCON_PORTB_PU_B13_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B13_BITS_ENABLE (PORTCON_PORTB_PU_B13_VALUE_ENABLE << PORTCON_PORTB_PU_B13_SHIFT) - -#define PORTCON_PORTB_PU_B14_SHIFT 14 -#define PORTCON_PORTB_PU_B14_WIDTH 1 -#define PORTCON_PORTB_PU_B14_MASK (((1U << PORTCON_PORTB_PU_B14_WIDTH) - 1U) << PORTCON_PORTB_PU_B14_SHIFT) -#define PORTCON_PORTB_PU_B14_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B14_BITS_DISABLE (PORTCON_PORTB_PU_B14_VALUE_DISABLE << PORTCON_PORTB_PU_B14_SHIFT) -#define PORTCON_PORTB_PU_B14_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B14_BITS_ENABLE (PORTCON_PORTB_PU_B14_VALUE_ENABLE << PORTCON_PORTB_PU_B14_SHIFT) - -#define PORTCON_PORTB_PU_B15_SHIFT 15 -#define PORTCON_PORTB_PU_B15_WIDTH 1 -#define PORTCON_PORTB_PU_B15_MASK (((1U << PORTCON_PORTB_PU_B15_WIDTH) - 1U) << PORTCON_PORTB_PU_B15_SHIFT) -#define PORTCON_PORTB_PU_B15_VALUE_DISABLE 0U -#define PORTCON_PORTB_PU_B15_BITS_DISABLE (PORTCON_PORTB_PU_B15_VALUE_DISABLE << PORTCON_PORTB_PU_B15_SHIFT) -#define PORTCON_PORTB_PU_B15_VALUE_ENABLE 1U -#define PORTCON_PORTB_PU_B15_BITS_ENABLE (PORTCON_PORTB_PU_B15_VALUE_ENABLE << PORTCON_PORTB_PU_B15_SHIFT) - -#define PORTCON_PORTC_PU_ADDR (PORTCON_BASE_ADDR + 0x0208U) -#define PORTCON_PORTC_PU (*(volatile uint32_t *)PORTCON_PORTC_PU_ADDR) -#define PORTCON_PORTC_PU_C0_SHIFT 0 -#define PORTCON_PORTC_PU_C0_WIDTH 1 -#define PORTCON_PORTC_PU_C0_MASK (((1U << PORTCON_PORTC_PU_C0_WIDTH) - 1U) << PORTCON_PORTC_PU_C0_SHIFT) -#define PORTCON_PORTC_PU_C0_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C0_BITS_DISABLE (PORTCON_PORTC_PU_C0_VALUE_DISABLE << PORTCON_PORTC_PU_C0_SHIFT) -#define PORTCON_PORTC_PU_C0_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C0_BITS_ENABLE (PORTCON_PORTC_PU_C0_VALUE_ENABLE << PORTCON_PORTC_PU_C0_SHIFT) - -#define PORTCON_PORTC_PU_C1_SHIFT 1 -#define PORTCON_PORTC_PU_C1_WIDTH 1 -#define PORTCON_PORTC_PU_C1_MASK (((1U << PORTCON_PORTC_PU_C1_WIDTH) - 1U) << PORTCON_PORTC_PU_C1_SHIFT) -#define PORTCON_PORTC_PU_C1_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C1_BITS_DISABLE (PORTCON_PORTC_PU_C1_VALUE_DISABLE << PORTCON_PORTC_PU_C1_SHIFT) -#define PORTCON_PORTC_PU_C1_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C1_BITS_ENABLE (PORTCON_PORTC_PU_C1_VALUE_ENABLE << PORTCON_PORTC_PU_C1_SHIFT) - -#define PORTCON_PORTC_PU_C2_SHIFT 2 -#define PORTCON_PORTC_PU_C2_WIDTH 1 -#define PORTCON_PORTC_PU_C2_MASK (((1U << PORTCON_PORTC_PU_C2_WIDTH) - 1U) << PORTCON_PORTC_PU_C2_SHIFT) -#define PORTCON_PORTC_PU_C2_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C2_BITS_DISABLE (PORTCON_PORTC_PU_C2_VALUE_DISABLE << PORTCON_PORTC_PU_C2_SHIFT) -#define PORTCON_PORTC_PU_C2_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C2_BITS_ENABLE (PORTCON_PORTC_PU_C2_VALUE_ENABLE << PORTCON_PORTC_PU_C2_SHIFT) - -#define PORTCON_PORTC_PU_C3_SHIFT 3 -#define PORTCON_PORTC_PU_C3_WIDTH 1 -#define PORTCON_PORTC_PU_C3_MASK (((1U << PORTCON_PORTC_PU_C3_WIDTH) - 1U) << PORTCON_PORTC_PU_C3_SHIFT) -#define PORTCON_PORTC_PU_C3_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C3_BITS_DISABLE (PORTCON_PORTC_PU_C3_VALUE_DISABLE << PORTCON_PORTC_PU_C3_SHIFT) -#define PORTCON_PORTC_PU_C3_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C3_BITS_ENABLE (PORTCON_PORTC_PU_C3_VALUE_ENABLE << PORTCON_PORTC_PU_C3_SHIFT) - -#define PORTCON_PORTC_PU_C4_SHIFT 4 -#define PORTCON_PORTC_PU_C4_WIDTH 1 -#define PORTCON_PORTC_PU_C4_MASK (((1U << PORTCON_PORTC_PU_C4_WIDTH) - 1U) << PORTCON_PORTC_PU_C4_SHIFT) -#define PORTCON_PORTC_PU_C4_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C4_BITS_DISABLE (PORTCON_PORTC_PU_C4_VALUE_DISABLE << PORTCON_PORTC_PU_C4_SHIFT) -#define PORTCON_PORTC_PU_C4_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C4_BITS_ENABLE (PORTCON_PORTC_PU_C4_VALUE_ENABLE << PORTCON_PORTC_PU_C4_SHIFT) - -#define PORTCON_PORTC_PU_C5_SHIFT 5 -#define PORTCON_PORTC_PU_C5_WIDTH 1 -#define PORTCON_PORTC_PU_C5_MASK (((1U << PORTCON_PORTC_PU_C5_WIDTH) - 1U) << PORTCON_PORTC_PU_C5_SHIFT) -#define PORTCON_PORTC_PU_C5_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C5_BITS_DISABLE (PORTCON_PORTC_PU_C5_VALUE_DISABLE << PORTCON_PORTC_PU_C5_SHIFT) -#define PORTCON_PORTC_PU_C5_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C5_BITS_ENABLE (PORTCON_PORTC_PU_C5_VALUE_ENABLE << PORTCON_PORTC_PU_C5_SHIFT) - -#define PORTCON_PORTC_PU_C6_SHIFT 6 -#define PORTCON_PORTC_PU_C6_WIDTH 1 -#define PORTCON_PORTC_PU_C6_MASK (((1U << PORTCON_PORTC_PU_C6_WIDTH) - 1U) << PORTCON_PORTC_PU_C6_SHIFT) -#define PORTCON_PORTC_PU_C6_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C6_BITS_DISABLE (PORTCON_PORTC_PU_C6_VALUE_DISABLE << PORTCON_PORTC_PU_C6_SHIFT) -#define PORTCON_PORTC_PU_C6_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C6_BITS_ENABLE (PORTCON_PORTC_PU_C6_VALUE_ENABLE << PORTCON_PORTC_PU_C6_SHIFT) - -#define PORTCON_PORTC_PU_C7_SHIFT 7 -#define PORTCON_PORTC_PU_C7_WIDTH 1 -#define PORTCON_PORTC_PU_C7_MASK (((1U << PORTCON_PORTC_PU_C7_WIDTH) - 1U) << PORTCON_PORTC_PU_C7_SHIFT) -#define PORTCON_PORTC_PU_C7_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C7_BITS_DISABLE (PORTCON_PORTC_PU_C7_VALUE_DISABLE << PORTCON_PORTC_PU_C7_SHIFT) -#define PORTCON_PORTC_PU_C7_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C7_BITS_ENABLE (PORTCON_PORTC_PU_C7_VALUE_ENABLE << PORTCON_PORTC_PU_C7_SHIFT) - -#define PORTCON_PORTC_PU_C8_SHIFT 8 -#define PORTCON_PORTC_PU_C8_WIDTH 1 -#define PORTCON_PORTC_PU_C8_MASK (((1U << PORTCON_PORTC_PU_C8_WIDTH) - 1U) << PORTCON_PORTC_PU_C8_SHIFT) -#define PORTCON_PORTC_PU_C8_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C8_BITS_DISABLE (PORTCON_PORTC_PU_C8_VALUE_DISABLE << PORTCON_PORTC_PU_C8_SHIFT) -#define PORTCON_PORTC_PU_C8_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C8_BITS_ENABLE (PORTCON_PORTC_PU_C8_VALUE_ENABLE << PORTCON_PORTC_PU_C8_SHIFT) - -#define PORTCON_PORTC_PU_C9_SHIFT 9 -#define PORTCON_PORTC_PU_C9_WIDTH 1 -#define PORTCON_PORTC_PU_C9_MASK (((1U << PORTCON_PORTC_PU_C9_WIDTH) - 1U) << PORTCON_PORTC_PU_C9_SHIFT) -#define PORTCON_PORTC_PU_C9_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C9_BITS_DISABLE (PORTCON_PORTC_PU_C9_VALUE_DISABLE << PORTCON_PORTC_PU_C9_SHIFT) -#define PORTCON_PORTC_PU_C9_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C9_BITS_ENABLE (PORTCON_PORTC_PU_C9_VALUE_ENABLE << PORTCON_PORTC_PU_C9_SHIFT) - -#define PORTCON_PORTC_PU_C10_SHIFT 10 -#define PORTCON_PORTC_PU_C10_WIDTH 1 -#define PORTCON_PORTC_PU_C10_MASK (((1U << PORTCON_PORTC_PU_C10_WIDTH) - 1U) << PORTCON_PORTC_PU_C10_SHIFT) -#define PORTCON_PORTC_PU_C10_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C10_BITS_DISABLE (PORTCON_PORTC_PU_C10_VALUE_DISABLE << PORTCON_PORTC_PU_C10_SHIFT) -#define PORTCON_PORTC_PU_C10_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C10_BITS_ENABLE (PORTCON_PORTC_PU_C10_VALUE_ENABLE << PORTCON_PORTC_PU_C10_SHIFT) - -#define PORTCON_PORTC_PU_C11_SHIFT 11 -#define PORTCON_PORTC_PU_C11_WIDTH 1 -#define PORTCON_PORTC_PU_C11_MASK (((1U << PORTCON_PORTC_PU_C11_WIDTH) - 1U) << PORTCON_PORTC_PU_C11_SHIFT) -#define PORTCON_PORTC_PU_C11_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C11_BITS_DISABLE (PORTCON_PORTC_PU_C11_VALUE_DISABLE << PORTCON_PORTC_PU_C11_SHIFT) -#define PORTCON_PORTC_PU_C11_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C11_BITS_ENABLE (PORTCON_PORTC_PU_C11_VALUE_ENABLE << PORTCON_PORTC_PU_C11_SHIFT) - -#define PORTCON_PORTC_PU_C12_SHIFT 12 -#define PORTCON_PORTC_PU_C12_WIDTH 1 -#define PORTCON_PORTC_PU_C12_MASK (((1U << PORTCON_PORTC_PU_C12_WIDTH) - 1U) << PORTCON_PORTC_PU_C12_SHIFT) -#define PORTCON_PORTC_PU_C12_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C12_BITS_DISABLE (PORTCON_PORTC_PU_C12_VALUE_DISABLE << PORTCON_PORTC_PU_C12_SHIFT) -#define PORTCON_PORTC_PU_C12_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C12_BITS_ENABLE (PORTCON_PORTC_PU_C12_VALUE_ENABLE << PORTCON_PORTC_PU_C12_SHIFT) - -#define PORTCON_PORTC_PU_C13_SHIFT 13 -#define PORTCON_PORTC_PU_C13_WIDTH 1 -#define PORTCON_PORTC_PU_C13_MASK (((1U << PORTCON_PORTC_PU_C13_WIDTH) - 1U) << PORTCON_PORTC_PU_C13_SHIFT) -#define PORTCON_PORTC_PU_C13_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C13_BITS_DISABLE (PORTCON_PORTC_PU_C13_VALUE_DISABLE << PORTCON_PORTC_PU_C13_SHIFT) -#define PORTCON_PORTC_PU_C13_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C13_BITS_ENABLE (PORTCON_PORTC_PU_C13_VALUE_ENABLE << PORTCON_PORTC_PU_C13_SHIFT) - -#define PORTCON_PORTC_PU_C14_SHIFT 14 -#define PORTCON_PORTC_PU_C14_WIDTH 1 -#define PORTCON_PORTC_PU_C14_MASK (((1U << PORTCON_PORTC_PU_C14_WIDTH) - 1U) << PORTCON_PORTC_PU_C14_SHIFT) -#define PORTCON_PORTC_PU_C14_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C14_BITS_DISABLE (PORTCON_PORTC_PU_C14_VALUE_DISABLE << PORTCON_PORTC_PU_C14_SHIFT) -#define PORTCON_PORTC_PU_C14_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C14_BITS_ENABLE (PORTCON_PORTC_PU_C14_VALUE_ENABLE << PORTCON_PORTC_PU_C14_SHIFT) - -#define PORTCON_PORTC_PU_C15_SHIFT 15 -#define PORTCON_PORTC_PU_C15_WIDTH 1 -#define PORTCON_PORTC_PU_C15_MASK (((1U << PORTCON_PORTC_PU_C15_WIDTH) - 1U) << PORTCON_PORTC_PU_C15_SHIFT) -#define PORTCON_PORTC_PU_C15_VALUE_DISABLE 0U -#define PORTCON_PORTC_PU_C15_BITS_DISABLE (PORTCON_PORTC_PU_C15_VALUE_DISABLE << PORTCON_PORTC_PU_C15_SHIFT) -#define PORTCON_PORTC_PU_C15_VALUE_ENABLE 1U -#define PORTCON_PORTC_PU_C15_BITS_ENABLE (PORTCON_PORTC_PU_C15_VALUE_ENABLE << PORTCON_PORTC_PU_C15_SHIFT) - -#define PORTCON_PORTA_PD_ADDR (PORTCON_BASE_ADDR + 0x0300U) -#define PORTCON_PORTA_PD (*(volatile uint32_t *)PORTCON_PORTA_PD_ADDR) -#define PORTCON_PORTA_PD_A0_SHIFT 0 -#define PORTCON_PORTA_PD_A0_WIDTH 1 -#define PORTCON_PORTA_PD_A0_MASK (((1U << PORTCON_PORTA_PD_A0_WIDTH) - 1U) << PORTCON_PORTA_PD_A0_SHIFT) -#define PORTCON_PORTA_PD_A0_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A0_BITS_DISABLE (PORTCON_PORTA_PD_A0_VALUE_DISABLE << PORTCON_PORTA_PD_A0_SHIFT) -#define PORTCON_PORTA_PD_A0_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A0_BITS_ENABLE (PORTCON_PORTA_PD_A0_VALUE_ENABLE << PORTCON_PORTA_PD_A0_SHIFT) - -#define PORTCON_PORTA_PD_A1_SHIFT 1 -#define PORTCON_PORTA_PD_A1_WIDTH 1 -#define PORTCON_PORTA_PD_A1_MASK (((1U << PORTCON_PORTA_PD_A1_WIDTH) - 1U) << PORTCON_PORTA_PD_A1_SHIFT) -#define PORTCON_PORTA_PD_A1_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A1_BITS_DISABLE (PORTCON_PORTA_PD_A1_VALUE_DISABLE << PORTCON_PORTA_PD_A1_SHIFT) -#define PORTCON_PORTA_PD_A1_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A1_BITS_ENABLE (PORTCON_PORTA_PD_A1_VALUE_ENABLE << PORTCON_PORTA_PD_A1_SHIFT) - -#define PORTCON_PORTA_PD_A2_SHIFT 2 -#define PORTCON_PORTA_PD_A2_WIDTH 1 -#define PORTCON_PORTA_PD_A2_MASK (((1U << PORTCON_PORTA_PD_A2_WIDTH) - 1U) << PORTCON_PORTA_PD_A2_SHIFT) -#define PORTCON_PORTA_PD_A2_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A2_BITS_DISABLE (PORTCON_PORTA_PD_A2_VALUE_DISABLE << PORTCON_PORTA_PD_A2_SHIFT) -#define PORTCON_PORTA_PD_A2_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A2_BITS_ENABLE (PORTCON_PORTA_PD_A2_VALUE_ENABLE << PORTCON_PORTA_PD_A2_SHIFT) - -#define PORTCON_PORTA_PD_A3_SHIFT 3 -#define PORTCON_PORTA_PD_A3_WIDTH 1 -#define PORTCON_PORTA_PD_A3_MASK (((1U << PORTCON_PORTA_PD_A3_WIDTH) - 1U) << PORTCON_PORTA_PD_A3_SHIFT) -#define PORTCON_PORTA_PD_A3_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A3_BITS_DISABLE (PORTCON_PORTA_PD_A3_VALUE_DISABLE << PORTCON_PORTA_PD_A3_SHIFT) -#define PORTCON_PORTA_PD_A3_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A3_BITS_ENABLE (PORTCON_PORTA_PD_A3_VALUE_ENABLE << PORTCON_PORTA_PD_A3_SHIFT) - -#define PORTCON_PORTA_PD_A4_SHIFT 4 -#define PORTCON_PORTA_PD_A4_WIDTH 1 -#define PORTCON_PORTA_PD_A4_MASK (((1U << PORTCON_PORTA_PD_A4_WIDTH) - 1U) << PORTCON_PORTA_PD_A4_SHIFT) -#define PORTCON_PORTA_PD_A4_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A4_BITS_DISABLE (PORTCON_PORTA_PD_A4_VALUE_DISABLE << PORTCON_PORTA_PD_A4_SHIFT) -#define PORTCON_PORTA_PD_A4_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A4_BITS_ENABLE (PORTCON_PORTA_PD_A4_VALUE_ENABLE << PORTCON_PORTA_PD_A4_SHIFT) - -#define PORTCON_PORTA_PD_A5_SHIFT 5 -#define PORTCON_PORTA_PD_A5_WIDTH 1 -#define PORTCON_PORTA_PD_A5_MASK (((1U << PORTCON_PORTA_PD_A5_WIDTH) - 1U) << PORTCON_PORTA_PD_A5_SHIFT) -#define PORTCON_PORTA_PD_A5_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A5_BITS_DISABLE (PORTCON_PORTA_PD_A5_VALUE_DISABLE << PORTCON_PORTA_PD_A5_SHIFT) -#define PORTCON_PORTA_PD_A5_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A5_BITS_ENABLE (PORTCON_PORTA_PD_A5_VALUE_ENABLE << PORTCON_PORTA_PD_A5_SHIFT) - -#define PORTCON_PORTA_PD_A6_SHIFT 6 -#define PORTCON_PORTA_PD_A6_WIDTH 1 -#define PORTCON_PORTA_PD_A6_MASK (((1U << PORTCON_PORTA_PD_A6_WIDTH) - 1U) << PORTCON_PORTA_PD_A6_SHIFT) -#define PORTCON_PORTA_PD_A6_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A6_BITS_DISABLE (PORTCON_PORTA_PD_A6_VALUE_DISABLE << PORTCON_PORTA_PD_A6_SHIFT) -#define PORTCON_PORTA_PD_A6_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A6_BITS_ENABLE (PORTCON_PORTA_PD_A6_VALUE_ENABLE << PORTCON_PORTA_PD_A6_SHIFT) - -#define PORTCON_PORTA_PD_A7_SHIFT 7 -#define PORTCON_PORTA_PD_A7_WIDTH 1 -#define PORTCON_PORTA_PD_A7_MASK (((1U << PORTCON_PORTA_PD_A7_WIDTH) - 1U) << PORTCON_PORTA_PD_A7_SHIFT) -#define PORTCON_PORTA_PD_A7_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A7_BITS_DISABLE (PORTCON_PORTA_PD_A7_VALUE_DISABLE << PORTCON_PORTA_PD_A7_SHIFT) -#define PORTCON_PORTA_PD_A7_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A7_BITS_ENABLE (PORTCON_PORTA_PD_A7_VALUE_ENABLE << PORTCON_PORTA_PD_A7_SHIFT) - -#define PORTCON_PORTA_PD_A8_SHIFT 8 -#define PORTCON_PORTA_PD_A8_WIDTH 1 -#define PORTCON_PORTA_PD_A8_MASK (((1U << PORTCON_PORTA_PD_A8_WIDTH) - 1U) << PORTCON_PORTA_PD_A8_SHIFT) -#define PORTCON_PORTA_PD_A8_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A8_BITS_DISABLE (PORTCON_PORTA_PD_A8_VALUE_DISABLE << PORTCON_PORTA_PD_A8_SHIFT) -#define PORTCON_PORTA_PD_A8_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A8_BITS_ENABLE (PORTCON_PORTA_PD_A8_VALUE_ENABLE << PORTCON_PORTA_PD_A8_SHIFT) - -#define PORTCON_PORTA_PD_A9_SHIFT 9 -#define PORTCON_PORTA_PD_A9_WIDTH 1 -#define PORTCON_PORTA_PD_A9_MASK (((1U << PORTCON_PORTA_PD_A9_WIDTH) - 1U) << PORTCON_PORTA_PD_A9_SHIFT) -#define PORTCON_PORTA_PD_A9_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A9_BITS_DISABLE (PORTCON_PORTA_PD_A9_VALUE_DISABLE << PORTCON_PORTA_PD_A9_SHIFT) -#define PORTCON_PORTA_PD_A9_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A9_BITS_ENABLE (PORTCON_PORTA_PD_A9_VALUE_ENABLE << PORTCON_PORTA_PD_A9_SHIFT) - -#define PORTCON_PORTA_PD_A10_SHIFT 10 -#define PORTCON_PORTA_PD_A10_WIDTH 1 -#define PORTCON_PORTA_PD_A10_MASK (((1U << PORTCON_PORTA_PD_A10_WIDTH) - 1U) << PORTCON_PORTA_PD_A10_SHIFT) -#define PORTCON_PORTA_PD_A10_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A10_BITS_DISABLE (PORTCON_PORTA_PD_A10_VALUE_DISABLE << PORTCON_PORTA_PD_A10_SHIFT) -#define PORTCON_PORTA_PD_A10_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A10_BITS_ENABLE (PORTCON_PORTA_PD_A10_VALUE_ENABLE << PORTCON_PORTA_PD_A10_SHIFT) - -#define PORTCON_PORTA_PD_A11_SHIFT 11 -#define PORTCON_PORTA_PD_A11_WIDTH 1 -#define PORTCON_PORTA_PD_A11_MASK (((1U << PORTCON_PORTA_PD_A11_WIDTH) - 1U) << PORTCON_PORTA_PD_A11_SHIFT) -#define PORTCON_PORTA_PD_A11_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A11_BITS_DISABLE (PORTCON_PORTA_PD_A11_VALUE_DISABLE << PORTCON_PORTA_PD_A11_SHIFT) -#define PORTCON_PORTA_PD_A11_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A11_BITS_ENABLE (PORTCON_PORTA_PD_A11_VALUE_ENABLE << PORTCON_PORTA_PD_A11_SHIFT) - -#define PORTCON_PORTA_PD_A12_SHIFT 12 -#define PORTCON_PORTA_PD_A12_WIDTH 1 -#define PORTCON_PORTA_PD_A12_MASK (((1U << PORTCON_PORTA_PD_A12_WIDTH) - 1U) << PORTCON_PORTA_PD_A12_SHIFT) -#define PORTCON_PORTA_PD_A12_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A12_BITS_DISABLE (PORTCON_PORTA_PD_A12_VALUE_DISABLE << PORTCON_PORTA_PD_A12_SHIFT) -#define PORTCON_PORTA_PD_A12_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A12_BITS_ENABLE (PORTCON_PORTA_PD_A12_VALUE_ENABLE << PORTCON_PORTA_PD_A12_SHIFT) - -#define PORTCON_PORTA_PD_A13_SHIFT 13 -#define PORTCON_PORTA_PD_A13_WIDTH 1 -#define PORTCON_PORTA_PD_A13_MASK (((1U << PORTCON_PORTA_PD_A13_WIDTH) - 1U) << PORTCON_PORTA_PD_A13_SHIFT) -#define PORTCON_PORTA_PD_A13_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A13_BITS_DISABLE (PORTCON_PORTA_PD_A13_VALUE_DISABLE << PORTCON_PORTA_PD_A13_SHIFT) -#define PORTCON_PORTA_PD_A13_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A13_BITS_ENABLE (PORTCON_PORTA_PD_A13_VALUE_ENABLE << PORTCON_PORTA_PD_A13_SHIFT) - -#define PORTCON_PORTA_PD_A14_SHIFT 14 -#define PORTCON_PORTA_PD_A14_WIDTH 1 -#define PORTCON_PORTA_PD_A14_MASK (((1U << PORTCON_PORTA_PD_A14_WIDTH) - 1U) << PORTCON_PORTA_PD_A14_SHIFT) -#define PORTCON_PORTA_PD_A14_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A14_BITS_DISABLE (PORTCON_PORTA_PD_A14_VALUE_DISABLE << PORTCON_PORTA_PD_A14_SHIFT) -#define PORTCON_PORTA_PD_A14_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A14_BITS_ENABLE (PORTCON_PORTA_PD_A14_VALUE_ENABLE << PORTCON_PORTA_PD_A14_SHIFT) - -#define PORTCON_PORTA_PD_A15_SHIFT 15 -#define PORTCON_PORTA_PD_A15_WIDTH 1 -#define PORTCON_PORTA_PD_A15_MASK (((1U << PORTCON_PORTA_PD_A15_WIDTH) - 1U) << PORTCON_PORTA_PD_A15_SHIFT) -#define PORTCON_PORTA_PD_A15_VALUE_DISABLE 0U -#define PORTCON_PORTA_PD_A15_BITS_DISABLE (PORTCON_PORTA_PD_A15_VALUE_DISABLE << PORTCON_PORTA_PD_A15_SHIFT) -#define PORTCON_PORTA_PD_A15_VALUE_ENABLE 1U -#define PORTCON_PORTA_PD_A15_BITS_ENABLE (PORTCON_PORTA_PD_A15_VALUE_ENABLE << PORTCON_PORTA_PD_A15_SHIFT) - -#define PORTCON_PORTB_PD_ADDR (PORTCON_BASE_ADDR + 0x0304U) -#define PORTCON_PORTB_PD (*(volatile uint32_t *)PORTCON_PORTB_PD_ADDR) -#define PORTCON_PORTB_PD_B0_SHIFT 0 -#define PORTCON_PORTB_PD_B0_WIDTH 1 -#define PORTCON_PORTB_PD_B0_MASK (((1U << PORTCON_PORTB_PD_B0_WIDTH) - 1U) << PORTCON_PORTB_PD_B0_SHIFT) -#define PORTCON_PORTB_PD_B0_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B0_BITS_DISABLE (PORTCON_PORTB_PD_B0_VALUE_DISABLE << PORTCON_PORTB_PD_B0_SHIFT) -#define PORTCON_PORTB_PD_B0_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B0_BITS_ENABLE (PORTCON_PORTB_PD_B0_VALUE_ENABLE << PORTCON_PORTB_PD_B0_SHIFT) - -#define PORTCON_PORTB_PD_B1_SHIFT 1 -#define PORTCON_PORTB_PD_B1_WIDTH 1 -#define PORTCON_PORTB_PD_B1_MASK (((1U << PORTCON_PORTB_PD_B1_WIDTH) - 1U) << PORTCON_PORTB_PD_B1_SHIFT) -#define PORTCON_PORTB_PD_B1_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B1_BITS_DISABLE (PORTCON_PORTB_PD_B1_VALUE_DISABLE << PORTCON_PORTB_PD_B1_SHIFT) -#define PORTCON_PORTB_PD_B1_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B1_BITS_ENABLE (PORTCON_PORTB_PD_B1_VALUE_ENABLE << PORTCON_PORTB_PD_B1_SHIFT) - -#define PORTCON_PORTB_PD_B2_SHIFT 2 -#define PORTCON_PORTB_PD_B2_WIDTH 1 -#define PORTCON_PORTB_PD_B2_MASK (((1U << PORTCON_PORTB_PD_B2_WIDTH) - 1U) << PORTCON_PORTB_PD_B2_SHIFT) -#define PORTCON_PORTB_PD_B2_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B2_BITS_DISABLE (PORTCON_PORTB_PD_B2_VALUE_DISABLE << PORTCON_PORTB_PD_B2_SHIFT) -#define PORTCON_PORTB_PD_B2_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B2_BITS_ENABLE (PORTCON_PORTB_PD_B2_VALUE_ENABLE << PORTCON_PORTB_PD_B2_SHIFT) - -#define PORTCON_PORTB_PD_B3_SHIFT 3 -#define PORTCON_PORTB_PD_B3_WIDTH 1 -#define PORTCON_PORTB_PD_B3_MASK (((1U << PORTCON_PORTB_PD_B3_WIDTH) - 1U) << PORTCON_PORTB_PD_B3_SHIFT) -#define PORTCON_PORTB_PD_B3_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B3_BITS_DISABLE (PORTCON_PORTB_PD_B3_VALUE_DISABLE << PORTCON_PORTB_PD_B3_SHIFT) -#define PORTCON_PORTB_PD_B3_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B3_BITS_ENABLE (PORTCON_PORTB_PD_B3_VALUE_ENABLE << PORTCON_PORTB_PD_B3_SHIFT) - -#define PORTCON_PORTB_PD_B4_SHIFT 4 -#define PORTCON_PORTB_PD_B4_WIDTH 1 -#define PORTCON_PORTB_PD_B4_MASK (((1U << PORTCON_PORTB_PD_B4_WIDTH) - 1U) << PORTCON_PORTB_PD_B4_SHIFT) -#define PORTCON_PORTB_PD_B4_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B4_BITS_DISABLE (PORTCON_PORTB_PD_B4_VALUE_DISABLE << PORTCON_PORTB_PD_B4_SHIFT) -#define PORTCON_PORTB_PD_B4_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B4_BITS_ENABLE (PORTCON_PORTB_PD_B4_VALUE_ENABLE << PORTCON_PORTB_PD_B4_SHIFT) - -#define PORTCON_PORTB_PD_B5_SHIFT 5 -#define PORTCON_PORTB_PD_B5_WIDTH 1 -#define PORTCON_PORTB_PD_B5_MASK (((1U << PORTCON_PORTB_PD_B5_WIDTH) - 1U) << PORTCON_PORTB_PD_B5_SHIFT) -#define PORTCON_PORTB_PD_B5_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B5_BITS_DISABLE (PORTCON_PORTB_PD_B5_VALUE_DISABLE << PORTCON_PORTB_PD_B5_SHIFT) -#define PORTCON_PORTB_PD_B5_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B5_BITS_ENABLE (PORTCON_PORTB_PD_B5_VALUE_ENABLE << PORTCON_PORTB_PD_B5_SHIFT) - -#define PORTCON_PORTB_PD_B6_SHIFT 6 -#define PORTCON_PORTB_PD_B6_WIDTH 1 -#define PORTCON_PORTB_PD_B6_MASK (((1U << PORTCON_PORTB_PD_B6_WIDTH) - 1U) << PORTCON_PORTB_PD_B6_SHIFT) -#define PORTCON_PORTB_PD_B6_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B6_BITS_DISABLE (PORTCON_PORTB_PD_B6_VALUE_DISABLE << PORTCON_PORTB_PD_B6_SHIFT) -#define PORTCON_PORTB_PD_B6_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B6_BITS_ENABLE (PORTCON_PORTB_PD_B6_VALUE_ENABLE << PORTCON_PORTB_PD_B6_SHIFT) - -#define PORTCON_PORTB_PD_B7_SHIFT 7 -#define PORTCON_PORTB_PD_B7_WIDTH 1 -#define PORTCON_PORTB_PD_B7_MASK (((1U << PORTCON_PORTB_PD_B7_WIDTH) - 1U) << PORTCON_PORTB_PD_B7_SHIFT) -#define PORTCON_PORTB_PD_B7_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B7_BITS_DISABLE (PORTCON_PORTB_PD_B7_VALUE_DISABLE << PORTCON_PORTB_PD_B7_SHIFT) -#define PORTCON_PORTB_PD_B7_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B7_BITS_ENABLE (PORTCON_PORTB_PD_B7_VALUE_ENABLE << PORTCON_PORTB_PD_B7_SHIFT) - -#define PORTCON_PORTB_PD_B8_SHIFT 8 -#define PORTCON_PORTB_PD_B8_WIDTH 1 -#define PORTCON_PORTB_PD_B8_MASK (((1U << PORTCON_PORTB_PD_B8_WIDTH) - 1U) << PORTCON_PORTB_PD_B8_SHIFT) -#define PORTCON_PORTB_PD_B8_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B8_BITS_DISABLE (PORTCON_PORTB_PD_B8_VALUE_DISABLE << PORTCON_PORTB_PD_B8_SHIFT) -#define PORTCON_PORTB_PD_B8_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B8_BITS_ENABLE (PORTCON_PORTB_PD_B8_VALUE_ENABLE << PORTCON_PORTB_PD_B8_SHIFT) - -#define PORTCON_PORTB_PD_B9_SHIFT 9 -#define PORTCON_PORTB_PD_B9_WIDTH 1 -#define PORTCON_PORTB_PD_B9_MASK (((1U << PORTCON_PORTB_PD_B9_WIDTH) - 1U) << PORTCON_PORTB_PD_B9_SHIFT) -#define PORTCON_PORTB_PD_B9_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B9_BITS_DISABLE (PORTCON_PORTB_PD_B9_VALUE_DISABLE << PORTCON_PORTB_PD_B9_SHIFT) -#define PORTCON_PORTB_PD_B9_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B9_BITS_ENABLE (PORTCON_PORTB_PD_B9_VALUE_ENABLE << PORTCON_PORTB_PD_B9_SHIFT) - -#define PORTCON_PORTB_PD_B10_SHIFT 10 -#define PORTCON_PORTB_PD_B10_WIDTH 1 -#define PORTCON_PORTB_PD_B10_MASK (((1U << PORTCON_PORTB_PD_B10_WIDTH) - 1U) << PORTCON_PORTB_PD_B10_SHIFT) -#define PORTCON_PORTB_PD_B10_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B10_BITS_DISABLE (PORTCON_PORTB_PD_B10_VALUE_DISABLE << PORTCON_PORTB_PD_B10_SHIFT) -#define PORTCON_PORTB_PD_B10_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B10_BITS_ENABLE (PORTCON_PORTB_PD_B10_VALUE_ENABLE << PORTCON_PORTB_PD_B10_SHIFT) - -#define PORTCON_PORTB_PD_B11_SHIFT 11 -#define PORTCON_PORTB_PD_B11_WIDTH 1 -#define PORTCON_PORTB_PD_B11_MASK (((1U << PORTCON_PORTB_PD_B11_WIDTH) - 1U) << PORTCON_PORTB_PD_B11_SHIFT) -#define PORTCON_PORTB_PD_B11_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B11_BITS_DISABLE (PORTCON_PORTB_PD_B11_VALUE_DISABLE << PORTCON_PORTB_PD_B11_SHIFT) -#define PORTCON_PORTB_PD_B11_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B11_BITS_ENABLE (PORTCON_PORTB_PD_B11_VALUE_ENABLE << PORTCON_PORTB_PD_B11_SHIFT) - -#define PORTCON_PORTB_PD_B12_SHIFT 12 -#define PORTCON_PORTB_PD_B12_WIDTH 1 -#define PORTCON_PORTB_PD_B12_MASK (((1U << PORTCON_PORTB_PD_B12_WIDTH) - 1U) << PORTCON_PORTB_PD_B12_SHIFT) -#define PORTCON_PORTB_PD_B12_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B12_BITS_DISABLE (PORTCON_PORTB_PD_B12_VALUE_DISABLE << PORTCON_PORTB_PD_B12_SHIFT) -#define PORTCON_PORTB_PD_B12_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B12_BITS_ENABLE (PORTCON_PORTB_PD_B12_VALUE_ENABLE << PORTCON_PORTB_PD_B12_SHIFT) - -#define PORTCON_PORTB_PD_B13_SHIFT 13 -#define PORTCON_PORTB_PD_B13_WIDTH 1 -#define PORTCON_PORTB_PD_B13_MASK (((1U << PORTCON_PORTB_PD_B13_WIDTH) - 1U) << PORTCON_PORTB_PD_B13_SHIFT) -#define PORTCON_PORTB_PD_B13_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B13_BITS_DISABLE (PORTCON_PORTB_PD_B13_VALUE_DISABLE << PORTCON_PORTB_PD_B13_SHIFT) -#define PORTCON_PORTB_PD_B13_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B13_BITS_ENABLE (PORTCON_PORTB_PD_B13_VALUE_ENABLE << PORTCON_PORTB_PD_B13_SHIFT) - -#define PORTCON_PORTB_PD_B14_SHIFT 14 -#define PORTCON_PORTB_PD_B14_WIDTH 1 -#define PORTCON_PORTB_PD_B14_MASK (((1U << PORTCON_PORTB_PD_B14_WIDTH) - 1U) << PORTCON_PORTB_PD_B14_SHIFT) -#define PORTCON_PORTB_PD_B14_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B14_BITS_DISABLE (PORTCON_PORTB_PD_B14_VALUE_DISABLE << PORTCON_PORTB_PD_B14_SHIFT) -#define PORTCON_PORTB_PD_B14_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B14_BITS_ENABLE (PORTCON_PORTB_PD_B14_VALUE_ENABLE << PORTCON_PORTB_PD_B14_SHIFT) - -#define PORTCON_PORTB_PD_B15_SHIFT 15 -#define PORTCON_PORTB_PD_B15_WIDTH 1 -#define PORTCON_PORTB_PD_B15_MASK (((1U << PORTCON_PORTB_PD_B15_WIDTH) - 1U) << PORTCON_PORTB_PD_B15_SHIFT) -#define PORTCON_PORTB_PD_B15_VALUE_DISABLE 0U -#define PORTCON_PORTB_PD_B15_BITS_DISABLE (PORTCON_PORTB_PD_B15_VALUE_DISABLE << PORTCON_PORTB_PD_B15_SHIFT) -#define PORTCON_PORTB_PD_B15_VALUE_ENABLE 1U -#define PORTCON_PORTB_PD_B15_BITS_ENABLE (PORTCON_PORTB_PD_B15_VALUE_ENABLE << PORTCON_PORTB_PD_B15_SHIFT) - -#define PORTCON_PORTC_PD_ADDR (PORTCON_BASE_ADDR + 0x0308U) -#define PORTCON_PORTC_PD (*(volatile uint32_t *)PORTCON_PORTC_PD_ADDR) -#define PORTCON_PORTC_PD_C0_SHIFT 0 -#define PORTCON_PORTC_PD_C0_WIDTH 1 -#define PORTCON_PORTC_PD_C0_MASK (((1U << PORTCON_PORTC_PD_C0_WIDTH) - 1U) << PORTCON_PORTC_PD_C0_SHIFT) -#define PORTCON_PORTC_PD_C0_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C0_BITS_DISABLE (PORTCON_PORTC_PD_C0_VALUE_DISABLE << PORTCON_PORTC_PD_C0_SHIFT) -#define PORTCON_PORTC_PD_C0_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C0_BITS_ENABLE (PORTCON_PORTC_PD_C0_VALUE_ENABLE << PORTCON_PORTC_PD_C0_SHIFT) - -#define PORTCON_PORTC_PD_C1_SHIFT 1 -#define PORTCON_PORTC_PD_C1_WIDTH 1 -#define PORTCON_PORTC_PD_C1_MASK (((1U << PORTCON_PORTC_PD_C1_WIDTH) - 1U) << PORTCON_PORTC_PD_C1_SHIFT) -#define PORTCON_PORTC_PD_C1_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C1_BITS_DISABLE (PORTCON_PORTC_PD_C1_VALUE_DISABLE << PORTCON_PORTC_PD_C1_SHIFT) -#define PORTCON_PORTC_PD_C1_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C1_BITS_ENABLE (PORTCON_PORTC_PD_C1_VALUE_ENABLE << PORTCON_PORTC_PD_C1_SHIFT) - -#define PORTCON_PORTC_PD_C2_SHIFT 2 -#define PORTCON_PORTC_PD_C2_WIDTH 1 -#define PORTCON_PORTC_PD_C2_MASK (((1U << PORTCON_PORTC_PD_C2_WIDTH) - 1U) << PORTCON_PORTC_PD_C2_SHIFT) -#define PORTCON_PORTC_PD_C2_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C2_BITS_DISABLE (PORTCON_PORTC_PD_C2_VALUE_DISABLE << PORTCON_PORTC_PD_C2_SHIFT) -#define PORTCON_PORTC_PD_C2_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C2_BITS_ENABLE (PORTCON_PORTC_PD_C2_VALUE_ENABLE << PORTCON_PORTC_PD_C2_SHIFT) - -#define PORTCON_PORTC_PD_C3_SHIFT 3 -#define PORTCON_PORTC_PD_C3_WIDTH 1 -#define PORTCON_PORTC_PD_C3_MASK (((1U << PORTCON_PORTC_PD_C3_WIDTH) - 1U) << PORTCON_PORTC_PD_C3_SHIFT) -#define PORTCON_PORTC_PD_C3_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C3_BITS_DISABLE (PORTCON_PORTC_PD_C3_VALUE_DISABLE << PORTCON_PORTC_PD_C3_SHIFT) -#define PORTCON_PORTC_PD_C3_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C3_BITS_ENABLE (PORTCON_PORTC_PD_C3_VALUE_ENABLE << PORTCON_PORTC_PD_C3_SHIFT) - -#define PORTCON_PORTC_PD_C4_SHIFT 4 -#define PORTCON_PORTC_PD_C4_WIDTH 1 -#define PORTCON_PORTC_PD_C4_MASK (((1U << PORTCON_PORTC_PD_C4_WIDTH) - 1U) << PORTCON_PORTC_PD_C4_SHIFT) -#define PORTCON_PORTC_PD_C4_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C4_BITS_DISABLE (PORTCON_PORTC_PD_C4_VALUE_DISABLE << PORTCON_PORTC_PD_C4_SHIFT) -#define PORTCON_PORTC_PD_C4_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C4_BITS_ENABLE (PORTCON_PORTC_PD_C4_VALUE_ENABLE << PORTCON_PORTC_PD_C4_SHIFT) - -#define PORTCON_PORTC_PD_C5_SHIFT 5 -#define PORTCON_PORTC_PD_C5_WIDTH 1 -#define PORTCON_PORTC_PD_C5_MASK (((1U << PORTCON_PORTC_PD_C5_WIDTH) - 1U) << PORTCON_PORTC_PD_C5_SHIFT) -#define PORTCON_PORTC_PD_C5_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C5_BITS_DISABLE (PORTCON_PORTC_PD_C5_VALUE_DISABLE << PORTCON_PORTC_PD_C5_SHIFT) -#define PORTCON_PORTC_PD_C5_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C5_BITS_ENABLE (PORTCON_PORTC_PD_C5_VALUE_ENABLE << PORTCON_PORTC_PD_C5_SHIFT) - -#define PORTCON_PORTC_PD_C6_SHIFT 6 -#define PORTCON_PORTC_PD_C6_WIDTH 1 -#define PORTCON_PORTC_PD_C6_MASK (((1U << PORTCON_PORTC_PD_C6_WIDTH) - 1U) << PORTCON_PORTC_PD_C6_SHIFT) -#define PORTCON_PORTC_PD_C6_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C6_BITS_DISABLE (PORTCON_PORTC_PD_C6_VALUE_DISABLE << PORTCON_PORTC_PD_C6_SHIFT) -#define PORTCON_PORTC_PD_C6_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C6_BITS_ENABLE (PORTCON_PORTC_PD_C6_VALUE_ENABLE << PORTCON_PORTC_PD_C6_SHIFT) - -#define PORTCON_PORTC_PD_C7_SHIFT 7 -#define PORTCON_PORTC_PD_C7_WIDTH 1 -#define PORTCON_PORTC_PD_C7_MASK (((1U << PORTCON_PORTC_PD_C7_WIDTH) - 1U) << PORTCON_PORTC_PD_C7_SHIFT) -#define PORTCON_PORTC_PD_C7_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C7_BITS_DISABLE (PORTCON_PORTC_PD_C7_VALUE_DISABLE << PORTCON_PORTC_PD_C7_SHIFT) -#define PORTCON_PORTC_PD_C7_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C7_BITS_ENABLE (PORTCON_PORTC_PD_C7_VALUE_ENABLE << PORTCON_PORTC_PD_C7_SHIFT) - -#define PORTCON_PORTC_PD_C8_SHIFT 8 -#define PORTCON_PORTC_PD_C8_WIDTH 1 -#define PORTCON_PORTC_PD_C8_MASK (((1U << PORTCON_PORTC_PD_C8_WIDTH) - 1U) << PORTCON_PORTC_PD_C8_SHIFT) -#define PORTCON_PORTC_PD_C8_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C8_BITS_DISABLE (PORTCON_PORTC_PD_C8_VALUE_DISABLE << PORTCON_PORTC_PD_C8_SHIFT) -#define PORTCON_PORTC_PD_C8_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C8_BITS_ENABLE (PORTCON_PORTC_PD_C8_VALUE_ENABLE << PORTCON_PORTC_PD_C8_SHIFT) - -#define PORTCON_PORTC_PD_C9_SHIFT 9 -#define PORTCON_PORTC_PD_C9_WIDTH 1 -#define PORTCON_PORTC_PD_C9_MASK (((1U << PORTCON_PORTC_PD_C9_WIDTH) - 1U) << PORTCON_PORTC_PD_C9_SHIFT) -#define PORTCON_PORTC_PD_C9_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C9_BITS_DISABLE (PORTCON_PORTC_PD_C9_VALUE_DISABLE << PORTCON_PORTC_PD_C9_SHIFT) -#define PORTCON_PORTC_PD_C9_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C9_BITS_ENABLE (PORTCON_PORTC_PD_C9_VALUE_ENABLE << PORTCON_PORTC_PD_C9_SHIFT) - -#define PORTCON_PORTC_PD_C10_SHIFT 10 -#define PORTCON_PORTC_PD_C10_WIDTH 1 -#define PORTCON_PORTC_PD_C10_MASK (((1U << PORTCON_PORTC_PD_C10_WIDTH) - 1U) << PORTCON_PORTC_PD_C10_SHIFT) -#define PORTCON_PORTC_PD_C10_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C10_BITS_DISABLE (PORTCON_PORTC_PD_C10_VALUE_DISABLE << PORTCON_PORTC_PD_C10_SHIFT) -#define PORTCON_PORTC_PD_C10_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C10_BITS_ENABLE (PORTCON_PORTC_PD_C10_VALUE_ENABLE << PORTCON_PORTC_PD_C10_SHIFT) - -#define PORTCON_PORTC_PD_C11_SHIFT 11 -#define PORTCON_PORTC_PD_C11_WIDTH 1 -#define PORTCON_PORTC_PD_C11_MASK (((1U << PORTCON_PORTC_PD_C11_WIDTH) - 1U) << PORTCON_PORTC_PD_C11_SHIFT) -#define PORTCON_PORTC_PD_C11_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C11_BITS_DISABLE (PORTCON_PORTC_PD_C11_VALUE_DISABLE << PORTCON_PORTC_PD_C11_SHIFT) -#define PORTCON_PORTC_PD_C11_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C11_BITS_ENABLE (PORTCON_PORTC_PD_C11_VALUE_ENABLE << PORTCON_PORTC_PD_C11_SHIFT) - -#define PORTCON_PORTC_PD_C12_SHIFT 12 -#define PORTCON_PORTC_PD_C12_WIDTH 1 -#define PORTCON_PORTC_PD_C12_MASK (((1U << PORTCON_PORTC_PD_C12_WIDTH) - 1U) << PORTCON_PORTC_PD_C12_SHIFT) -#define PORTCON_PORTC_PD_C12_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C12_BITS_DISABLE (PORTCON_PORTC_PD_C12_VALUE_DISABLE << PORTCON_PORTC_PD_C12_SHIFT) -#define PORTCON_PORTC_PD_C12_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C12_BITS_ENABLE (PORTCON_PORTC_PD_C12_VALUE_ENABLE << PORTCON_PORTC_PD_C12_SHIFT) - -#define PORTCON_PORTC_PD_C13_SHIFT 13 -#define PORTCON_PORTC_PD_C13_WIDTH 1 -#define PORTCON_PORTC_PD_C13_MASK (((1U << PORTCON_PORTC_PD_C13_WIDTH) - 1U) << PORTCON_PORTC_PD_C13_SHIFT) -#define PORTCON_PORTC_PD_C13_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C13_BITS_DISABLE (PORTCON_PORTC_PD_C13_VALUE_DISABLE << PORTCON_PORTC_PD_C13_SHIFT) -#define PORTCON_PORTC_PD_C13_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C13_BITS_ENABLE (PORTCON_PORTC_PD_C13_VALUE_ENABLE << PORTCON_PORTC_PD_C13_SHIFT) - -#define PORTCON_PORTC_PD_C14_SHIFT 14 -#define PORTCON_PORTC_PD_C14_WIDTH 1 -#define PORTCON_PORTC_PD_C14_MASK (((1U << PORTCON_PORTC_PD_C14_WIDTH) - 1U) << PORTCON_PORTC_PD_C14_SHIFT) -#define PORTCON_PORTC_PD_C14_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C14_BITS_DISABLE (PORTCON_PORTC_PD_C14_VALUE_DISABLE << PORTCON_PORTC_PD_C14_SHIFT) -#define PORTCON_PORTC_PD_C14_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C14_BITS_ENABLE (PORTCON_PORTC_PD_C14_VALUE_ENABLE << PORTCON_PORTC_PD_C14_SHIFT) - -#define PORTCON_PORTC_PD_C15_SHIFT 15 -#define PORTCON_PORTC_PD_C15_WIDTH 1 -#define PORTCON_PORTC_PD_C15_MASK (((1U << PORTCON_PORTC_PD_C15_WIDTH) - 1U) << PORTCON_PORTC_PD_C15_SHIFT) -#define PORTCON_PORTC_PD_C15_VALUE_DISABLE 0U -#define PORTCON_PORTC_PD_C15_BITS_DISABLE (PORTCON_PORTC_PD_C15_VALUE_DISABLE << PORTCON_PORTC_PD_C15_SHIFT) -#define PORTCON_PORTC_PD_C15_VALUE_ENABLE 1U -#define PORTCON_PORTC_PD_C15_BITS_ENABLE (PORTCON_PORTC_PD_C15_VALUE_ENABLE << PORTCON_PORTC_PD_C15_SHIFT) - -#define PORTCON_PORTA_OD_ADDR (PORTCON_BASE_ADDR + 0x0400U) -#define PORTCON_PORTA_OD (*(volatile uint32_t *)PORTCON_PORTA_OD_ADDR) -#define PORTCON_PORTA_OD_A0_SHIFT 0 -#define PORTCON_PORTA_OD_A0_WIDTH 1 -#define PORTCON_PORTA_OD_A0_MASK (((1U << PORTCON_PORTA_OD_A0_WIDTH) - 1U) << PORTCON_PORTA_OD_A0_SHIFT) -#define PORTCON_PORTA_OD_A0_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A0_BITS_DISABLE (PORTCON_PORTA_OD_A0_VALUE_DISABLE << PORTCON_PORTA_OD_A0_SHIFT) -#define PORTCON_PORTA_OD_A0_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A0_BITS_ENABLE (PORTCON_PORTA_OD_A0_VALUE_ENABLE << PORTCON_PORTA_OD_A0_SHIFT) - -#define PORTCON_PORTA_OD_A1_SHIFT 1 -#define PORTCON_PORTA_OD_A1_WIDTH 1 -#define PORTCON_PORTA_OD_A1_MASK (((1U << PORTCON_PORTA_OD_A1_WIDTH) - 1U) << PORTCON_PORTA_OD_A1_SHIFT) -#define PORTCON_PORTA_OD_A1_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A1_BITS_DISABLE (PORTCON_PORTA_OD_A1_VALUE_DISABLE << PORTCON_PORTA_OD_A1_SHIFT) -#define PORTCON_PORTA_OD_A1_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A1_BITS_ENABLE (PORTCON_PORTA_OD_A1_VALUE_ENABLE << PORTCON_PORTA_OD_A1_SHIFT) - -#define PORTCON_PORTA_OD_A2_SHIFT 2 -#define PORTCON_PORTA_OD_A2_WIDTH 1 -#define PORTCON_PORTA_OD_A2_MASK (((1U << PORTCON_PORTA_OD_A2_WIDTH) - 1U) << PORTCON_PORTA_OD_A2_SHIFT) -#define PORTCON_PORTA_OD_A2_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A2_BITS_DISABLE (PORTCON_PORTA_OD_A2_VALUE_DISABLE << PORTCON_PORTA_OD_A2_SHIFT) -#define PORTCON_PORTA_OD_A2_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A2_BITS_ENABLE (PORTCON_PORTA_OD_A2_VALUE_ENABLE << PORTCON_PORTA_OD_A2_SHIFT) - -#define PORTCON_PORTA_OD_A3_SHIFT 3 -#define PORTCON_PORTA_OD_A3_WIDTH 1 -#define PORTCON_PORTA_OD_A3_MASK (((1U << PORTCON_PORTA_OD_A3_WIDTH) - 1U) << PORTCON_PORTA_OD_A3_SHIFT) -#define PORTCON_PORTA_OD_A3_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A3_BITS_DISABLE (PORTCON_PORTA_OD_A3_VALUE_DISABLE << PORTCON_PORTA_OD_A3_SHIFT) -#define PORTCON_PORTA_OD_A3_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A3_BITS_ENABLE (PORTCON_PORTA_OD_A3_VALUE_ENABLE << PORTCON_PORTA_OD_A3_SHIFT) - -#define PORTCON_PORTA_OD_A4_SHIFT 4 -#define PORTCON_PORTA_OD_A4_WIDTH 1 -#define PORTCON_PORTA_OD_A4_MASK (((1U << PORTCON_PORTA_OD_A4_WIDTH) - 1U) << PORTCON_PORTA_OD_A4_SHIFT) -#define PORTCON_PORTA_OD_A4_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A4_BITS_DISABLE (PORTCON_PORTA_OD_A4_VALUE_DISABLE << PORTCON_PORTA_OD_A4_SHIFT) -#define PORTCON_PORTA_OD_A4_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A4_BITS_ENABLE (PORTCON_PORTA_OD_A4_VALUE_ENABLE << PORTCON_PORTA_OD_A4_SHIFT) - -#define PORTCON_PORTA_OD_A5_SHIFT 5 -#define PORTCON_PORTA_OD_A5_WIDTH 1 -#define PORTCON_PORTA_OD_A5_MASK (((1U << PORTCON_PORTA_OD_A5_WIDTH) - 1U) << PORTCON_PORTA_OD_A5_SHIFT) -#define PORTCON_PORTA_OD_A5_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A5_BITS_DISABLE (PORTCON_PORTA_OD_A5_VALUE_DISABLE << PORTCON_PORTA_OD_A5_SHIFT) -#define PORTCON_PORTA_OD_A5_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A5_BITS_ENABLE (PORTCON_PORTA_OD_A5_VALUE_ENABLE << PORTCON_PORTA_OD_A5_SHIFT) - -#define PORTCON_PORTA_OD_A6_SHIFT 6 -#define PORTCON_PORTA_OD_A6_WIDTH 1 -#define PORTCON_PORTA_OD_A6_MASK (((1U << PORTCON_PORTA_OD_A6_WIDTH) - 1U) << PORTCON_PORTA_OD_A6_SHIFT) -#define PORTCON_PORTA_OD_A6_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A6_BITS_DISABLE (PORTCON_PORTA_OD_A6_VALUE_DISABLE << PORTCON_PORTA_OD_A6_SHIFT) -#define PORTCON_PORTA_OD_A6_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A6_BITS_ENABLE (PORTCON_PORTA_OD_A6_VALUE_ENABLE << PORTCON_PORTA_OD_A6_SHIFT) - -#define PORTCON_PORTA_OD_A7_SHIFT 7 -#define PORTCON_PORTA_OD_A7_WIDTH 1 -#define PORTCON_PORTA_OD_A7_MASK (((1U << PORTCON_PORTA_OD_A7_WIDTH) - 1U) << PORTCON_PORTA_OD_A7_SHIFT) -#define PORTCON_PORTA_OD_A7_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A7_BITS_DISABLE (PORTCON_PORTA_OD_A7_VALUE_DISABLE << PORTCON_PORTA_OD_A7_SHIFT) -#define PORTCON_PORTA_OD_A7_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A7_BITS_ENABLE (PORTCON_PORTA_OD_A7_VALUE_ENABLE << PORTCON_PORTA_OD_A7_SHIFT) - -#define PORTCON_PORTA_OD_A8_SHIFT 8 -#define PORTCON_PORTA_OD_A8_WIDTH 1 -#define PORTCON_PORTA_OD_A8_MASK (((1U << PORTCON_PORTA_OD_A8_WIDTH) - 1U) << PORTCON_PORTA_OD_A8_SHIFT) -#define PORTCON_PORTA_OD_A8_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A8_BITS_DISABLE (PORTCON_PORTA_OD_A8_VALUE_DISABLE << PORTCON_PORTA_OD_A8_SHIFT) -#define PORTCON_PORTA_OD_A8_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A8_BITS_ENABLE (PORTCON_PORTA_OD_A8_VALUE_ENABLE << PORTCON_PORTA_OD_A8_SHIFT) - -#define PORTCON_PORTA_OD_A9_SHIFT 9 -#define PORTCON_PORTA_OD_A9_WIDTH 1 -#define PORTCON_PORTA_OD_A9_MASK (((1U << PORTCON_PORTA_OD_A9_WIDTH) - 1U) << PORTCON_PORTA_OD_A9_SHIFT) -#define PORTCON_PORTA_OD_A9_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A9_BITS_DISABLE (PORTCON_PORTA_OD_A9_VALUE_DISABLE << PORTCON_PORTA_OD_A9_SHIFT) -#define PORTCON_PORTA_OD_A9_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A9_BITS_ENABLE (PORTCON_PORTA_OD_A9_VALUE_ENABLE << PORTCON_PORTA_OD_A9_SHIFT) - -#define PORTCON_PORTA_OD_A10_SHIFT 10 -#define PORTCON_PORTA_OD_A10_WIDTH 1 -#define PORTCON_PORTA_OD_A10_MASK (((1U << PORTCON_PORTA_OD_A10_WIDTH) - 1U) << PORTCON_PORTA_OD_A10_SHIFT) -#define PORTCON_PORTA_OD_A10_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A10_BITS_DISABLE (PORTCON_PORTA_OD_A10_VALUE_DISABLE << PORTCON_PORTA_OD_A10_SHIFT) -#define PORTCON_PORTA_OD_A10_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A10_BITS_ENABLE (PORTCON_PORTA_OD_A10_VALUE_ENABLE << PORTCON_PORTA_OD_A10_SHIFT) - -#define PORTCON_PORTA_OD_A11_SHIFT 11 -#define PORTCON_PORTA_OD_A11_WIDTH 1 -#define PORTCON_PORTA_OD_A11_MASK (((1U << PORTCON_PORTA_OD_A11_WIDTH) - 1U) << PORTCON_PORTA_OD_A11_SHIFT) -#define PORTCON_PORTA_OD_A11_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A11_BITS_DISABLE (PORTCON_PORTA_OD_A11_VALUE_DISABLE << PORTCON_PORTA_OD_A11_SHIFT) -#define PORTCON_PORTA_OD_A11_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A11_BITS_ENABLE (PORTCON_PORTA_OD_A11_VALUE_ENABLE << PORTCON_PORTA_OD_A11_SHIFT) - -#define PORTCON_PORTA_OD_A12_SHIFT 12 -#define PORTCON_PORTA_OD_A12_WIDTH 1 -#define PORTCON_PORTA_OD_A12_MASK (((1U << PORTCON_PORTA_OD_A12_WIDTH) - 1U) << PORTCON_PORTA_OD_A12_SHIFT) -#define PORTCON_PORTA_OD_A12_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A12_BITS_DISABLE (PORTCON_PORTA_OD_A12_VALUE_DISABLE << PORTCON_PORTA_OD_A12_SHIFT) -#define PORTCON_PORTA_OD_A12_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A12_BITS_ENABLE (PORTCON_PORTA_OD_A12_VALUE_ENABLE << PORTCON_PORTA_OD_A12_SHIFT) - -#define PORTCON_PORTA_OD_A13_SHIFT 13 -#define PORTCON_PORTA_OD_A13_WIDTH 1 -#define PORTCON_PORTA_OD_A13_MASK (((1U << PORTCON_PORTA_OD_A13_WIDTH) - 1U) << PORTCON_PORTA_OD_A13_SHIFT) -#define PORTCON_PORTA_OD_A13_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A13_BITS_DISABLE (PORTCON_PORTA_OD_A13_VALUE_DISABLE << PORTCON_PORTA_OD_A13_SHIFT) -#define PORTCON_PORTA_OD_A13_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A13_BITS_ENABLE (PORTCON_PORTA_OD_A13_VALUE_ENABLE << PORTCON_PORTA_OD_A13_SHIFT) - -#define PORTCON_PORTA_OD_A14_SHIFT 14 -#define PORTCON_PORTA_OD_A14_WIDTH 1 -#define PORTCON_PORTA_OD_A14_MASK (((1U << PORTCON_PORTA_OD_A14_WIDTH) - 1U) << PORTCON_PORTA_OD_A14_SHIFT) -#define PORTCON_PORTA_OD_A14_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A14_BITS_DISABLE (PORTCON_PORTA_OD_A14_VALUE_DISABLE << PORTCON_PORTA_OD_A14_SHIFT) -#define PORTCON_PORTA_OD_A14_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A14_BITS_ENABLE (PORTCON_PORTA_OD_A14_VALUE_ENABLE << PORTCON_PORTA_OD_A14_SHIFT) - -#define PORTCON_PORTA_OD_A15_SHIFT 15 -#define PORTCON_PORTA_OD_A15_WIDTH 1 -#define PORTCON_PORTA_OD_A15_MASK (((1U << PORTCON_PORTA_OD_A15_WIDTH) - 1U) << PORTCON_PORTA_OD_A15_SHIFT) -#define PORTCON_PORTA_OD_A15_VALUE_DISABLE 0U -#define PORTCON_PORTA_OD_A15_BITS_DISABLE (PORTCON_PORTA_OD_A15_VALUE_DISABLE << PORTCON_PORTA_OD_A15_SHIFT) -#define PORTCON_PORTA_OD_A15_VALUE_ENABLE 1U -#define PORTCON_PORTA_OD_A15_BITS_ENABLE (PORTCON_PORTA_OD_A15_VALUE_ENABLE << PORTCON_PORTA_OD_A15_SHIFT) - -#define PORTCON_PORTB_OD_ADDR (PORTCON_BASE_ADDR + 0x0404U) -#define PORTCON_PORTB_OD (*(volatile uint32_t *)PORTCON_PORTB_OD_ADDR) -#define PORTCON_PORTB_OD_B0_SHIFT 0 -#define PORTCON_PORTB_OD_B0_WIDTH 1 -#define PORTCON_PORTB_OD_B0_MASK (((1U << PORTCON_PORTB_OD_B0_WIDTH) - 1U) << PORTCON_PORTB_OD_B0_SHIFT) -#define PORTCON_PORTB_OD_B0_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B0_BITS_DISABLE (PORTCON_PORTB_OD_B0_VALUE_DISABLE << PORTCON_PORTB_OD_B0_SHIFT) -#define PORTCON_PORTB_OD_B0_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B0_BITS_ENABLE (PORTCON_PORTB_OD_B0_VALUE_ENABLE << PORTCON_PORTB_OD_B0_SHIFT) - -#define PORTCON_PORTB_OD_B1_SHIFT 1 -#define PORTCON_PORTB_OD_B1_WIDTH 1 -#define PORTCON_PORTB_OD_B1_MASK (((1U << PORTCON_PORTB_OD_B1_WIDTH) - 1U) << PORTCON_PORTB_OD_B1_SHIFT) -#define PORTCON_PORTB_OD_B1_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B1_BITS_DISABLE (PORTCON_PORTB_OD_B1_VALUE_DISABLE << PORTCON_PORTB_OD_B1_SHIFT) -#define PORTCON_PORTB_OD_B1_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B1_BITS_ENABLE (PORTCON_PORTB_OD_B1_VALUE_ENABLE << PORTCON_PORTB_OD_B1_SHIFT) - -#define PORTCON_PORTB_OD_B2_SHIFT 2 -#define PORTCON_PORTB_OD_B2_WIDTH 1 -#define PORTCON_PORTB_OD_B2_MASK (((1U << PORTCON_PORTB_OD_B2_WIDTH) - 1U) << PORTCON_PORTB_OD_B2_SHIFT) -#define PORTCON_PORTB_OD_B2_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B2_BITS_DISABLE (PORTCON_PORTB_OD_B2_VALUE_DISABLE << PORTCON_PORTB_OD_B2_SHIFT) -#define PORTCON_PORTB_OD_B2_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B2_BITS_ENABLE (PORTCON_PORTB_OD_B2_VALUE_ENABLE << PORTCON_PORTB_OD_B2_SHIFT) - -#define PORTCON_PORTB_OD_B3_SHIFT 3 -#define PORTCON_PORTB_OD_B3_WIDTH 1 -#define PORTCON_PORTB_OD_B3_MASK (((1U << PORTCON_PORTB_OD_B3_WIDTH) - 1U) << PORTCON_PORTB_OD_B3_SHIFT) -#define PORTCON_PORTB_OD_B3_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B3_BITS_DISABLE (PORTCON_PORTB_OD_B3_VALUE_DISABLE << PORTCON_PORTB_OD_B3_SHIFT) -#define PORTCON_PORTB_OD_B3_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B3_BITS_ENABLE (PORTCON_PORTB_OD_B3_VALUE_ENABLE << PORTCON_PORTB_OD_B3_SHIFT) - -#define PORTCON_PORTB_OD_B4_SHIFT 4 -#define PORTCON_PORTB_OD_B4_WIDTH 1 -#define PORTCON_PORTB_OD_B4_MASK (((1U << PORTCON_PORTB_OD_B4_WIDTH) - 1U) << PORTCON_PORTB_OD_B4_SHIFT) -#define PORTCON_PORTB_OD_B4_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B4_BITS_DISABLE (PORTCON_PORTB_OD_B4_VALUE_DISABLE << PORTCON_PORTB_OD_B4_SHIFT) -#define PORTCON_PORTB_OD_B4_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B4_BITS_ENABLE (PORTCON_PORTB_OD_B4_VALUE_ENABLE << PORTCON_PORTB_OD_B4_SHIFT) - -#define PORTCON_PORTB_OD_B5_SHIFT 5 -#define PORTCON_PORTB_OD_B5_WIDTH 1 -#define PORTCON_PORTB_OD_B5_MASK (((1U << PORTCON_PORTB_OD_B5_WIDTH) - 1U) << PORTCON_PORTB_OD_B5_SHIFT) -#define PORTCON_PORTB_OD_B5_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B5_BITS_DISABLE (PORTCON_PORTB_OD_B5_VALUE_DISABLE << PORTCON_PORTB_OD_B5_SHIFT) -#define PORTCON_PORTB_OD_B5_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B5_BITS_ENABLE (PORTCON_PORTB_OD_B5_VALUE_ENABLE << PORTCON_PORTB_OD_B5_SHIFT) - -#define PORTCON_PORTB_OD_B6_SHIFT 6 -#define PORTCON_PORTB_OD_B6_WIDTH 1 -#define PORTCON_PORTB_OD_B6_MASK (((1U << PORTCON_PORTB_OD_B6_WIDTH) - 1U) << PORTCON_PORTB_OD_B6_SHIFT) -#define PORTCON_PORTB_OD_B6_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B6_BITS_DISABLE (PORTCON_PORTB_OD_B6_VALUE_DISABLE << PORTCON_PORTB_OD_B6_SHIFT) -#define PORTCON_PORTB_OD_B6_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B6_BITS_ENABLE (PORTCON_PORTB_OD_B6_VALUE_ENABLE << PORTCON_PORTB_OD_B6_SHIFT) - -#define PORTCON_PORTB_OD_B7_SHIFT 7 -#define PORTCON_PORTB_OD_B7_WIDTH 1 -#define PORTCON_PORTB_OD_B7_MASK (((1U << PORTCON_PORTB_OD_B7_WIDTH) - 1U) << PORTCON_PORTB_OD_B7_SHIFT) -#define PORTCON_PORTB_OD_B7_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B7_BITS_DISABLE (PORTCON_PORTB_OD_B7_VALUE_DISABLE << PORTCON_PORTB_OD_B7_SHIFT) -#define PORTCON_PORTB_OD_B7_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B7_BITS_ENABLE (PORTCON_PORTB_OD_B7_VALUE_ENABLE << PORTCON_PORTB_OD_B7_SHIFT) - -#define PORTCON_PORTB_OD_B8_SHIFT 8 -#define PORTCON_PORTB_OD_B8_WIDTH 1 -#define PORTCON_PORTB_OD_B8_MASK (((1U << PORTCON_PORTB_OD_B8_WIDTH) - 1U) << PORTCON_PORTB_OD_B8_SHIFT) -#define PORTCON_PORTB_OD_B8_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B8_BITS_DISABLE (PORTCON_PORTB_OD_B8_VALUE_DISABLE << PORTCON_PORTB_OD_B8_SHIFT) -#define PORTCON_PORTB_OD_B8_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B8_BITS_ENABLE (PORTCON_PORTB_OD_B8_VALUE_ENABLE << PORTCON_PORTB_OD_B8_SHIFT) - -#define PORTCON_PORTB_OD_B9_SHIFT 9 -#define PORTCON_PORTB_OD_B9_WIDTH 1 -#define PORTCON_PORTB_OD_B9_MASK (((1U << PORTCON_PORTB_OD_B9_WIDTH) - 1U) << PORTCON_PORTB_OD_B9_SHIFT) -#define PORTCON_PORTB_OD_B9_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B9_BITS_DISABLE (PORTCON_PORTB_OD_B9_VALUE_DISABLE << PORTCON_PORTB_OD_B9_SHIFT) -#define PORTCON_PORTB_OD_B9_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B9_BITS_ENABLE (PORTCON_PORTB_OD_B9_VALUE_ENABLE << PORTCON_PORTB_OD_B9_SHIFT) - -#define PORTCON_PORTB_OD_B10_SHIFT 10 -#define PORTCON_PORTB_OD_B10_WIDTH 1 -#define PORTCON_PORTB_OD_B10_MASK (((1U << PORTCON_PORTB_OD_B10_WIDTH) - 1U) << PORTCON_PORTB_OD_B10_SHIFT) -#define PORTCON_PORTB_OD_B10_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B10_BITS_DISABLE (PORTCON_PORTB_OD_B10_VALUE_DISABLE << PORTCON_PORTB_OD_B10_SHIFT) -#define PORTCON_PORTB_OD_B10_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B10_BITS_ENABLE (PORTCON_PORTB_OD_B10_VALUE_ENABLE << PORTCON_PORTB_OD_B10_SHIFT) - -#define PORTCON_PORTB_OD_B11_SHIFT 11 -#define PORTCON_PORTB_OD_B11_WIDTH 1 -#define PORTCON_PORTB_OD_B11_MASK (((1U << PORTCON_PORTB_OD_B11_WIDTH) - 1U) << PORTCON_PORTB_OD_B11_SHIFT) -#define PORTCON_PORTB_OD_B11_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B11_BITS_DISABLE (PORTCON_PORTB_OD_B11_VALUE_DISABLE << PORTCON_PORTB_OD_B11_SHIFT) -#define PORTCON_PORTB_OD_B11_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B11_BITS_ENABLE (PORTCON_PORTB_OD_B11_VALUE_ENABLE << PORTCON_PORTB_OD_B11_SHIFT) - -#define PORTCON_PORTB_OD_B12_SHIFT 12 -#define PORTCON_PORTB_OD_B12_WIDTH 1 -#define PORTCON_PORTB_OD_B12_MASK (((1U << PORTCON_PORTB_OD_B12_WIDTH) - 1U) << PORTCON_PORTB_OD_B12_SHIFT) -#define PORTCON_PORTB_OD_B12_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B12_BITS_DISABLE (PORTCON_PORTB_OD_B12_VALUE_DISABLE << PORTCON_PORTB_OD_B12_SHIFT) -#define PORTCON_PORTB_OD_B12_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B12_BITS_ENABLE (PORTCON_PORTB_OD_B12_VALUE_ENABLE << PORTCON_PORTB_OD_B12_SHIFT) - -#define PORTCON_PORTB_OD_B13_SHIFT 13 -#define PORTCON_PORTB_OD_B13_WIDTH 1 -#define PORTCON_PORTB_OD_B13_MASK (((1U << PORTCON_PORTB_OD_B13_WIDTH) - 1U) << PORTCON_PORTB_OD_B13_SHIFT) -#define PORTCON_PORTB_OD_B13_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B13_BITS_DISABLE (PORTCON_PORTB_OD_B13_VALUE_DISABLE << PORTCON_PORTB_OD_B13_SHIFT) -#define PORTCON_PORTB_OD_B13_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B13_BITS_ENABLE (PORTCON_PORTB_OD_B13_VALUE_ENABLE << PORTCON_PORTB_OD_B13_SHIFT) - -#define PORTCON_PORTB_OD_B14_SHIFT 14 -#define PORTCON_PORTB_OD_B14_WIDTH 1 -#define PORTCON_PORTB_OD_B14_MASK (((1U << PORTCON_PORTB_OD_B14_WIDTH) - 1U) << PORTCON_PORTB_OD_B14_SHIFT) -#define PORTCON_PORTB_OD_B14_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B14_BITS_DISABLE (PORTCON_PORTB_OD_B14_VALUE_DISABLE << PORTCON_PORTB_OD_B14_SHIFT) -#define PORTCON_PORTB_OD_B14_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B14_BITS_ENABLE (PORTCON_PORTB_OD_B14_VALUE_ENABLE << PORTCON_PORTB_OD_B14_SHIFT) - -#define PORTCON_PORTB_OD_B15_SHIFT 15 -#define PORTCON_PORTB_OD_B15_WIDTH 1 -#define PORTCON_PORTB_OD_B15_MASK (((1U << PORTCON_PORTB_OD_B15_WIDTH) - 1U) << PORTCON_PORTB_OD_B15_SHIFT) -#define PORTCON_PORTB_OD_B15_VALUE_DISABLE 0U -#define PORTCON_PORTB_OD_B15_BITS_DISABLE (PORTCON_PORTB_OD_B15_VALUE_DISABLE << PORTCON_PORTB_OD_B15_SHIFT) -#define PORTCON_PORTB_OD_B15_VALUE_ENABLE 1U -#define PORTCON_PORTB_OD_B15_BITS_ENABLE (PORTCON_PORTB_OD_B15_VALUE_ENABLE << PORTCON_PORTB_OD_B15_SHIFT) - -#define PORTCON_PORTC_OD_ADDR (PORTCON_BASE_ADDR + 0x0408U) -#define PORTCON_PORTC_OD (*(volatile uint32_t *)PORTCON_PORTC_OD_ADDR) -#define PORTCON_PORTC_OD_C0_SHIFT 0 -#define PORTCON_PORTC_OD_C0_WIDTH 1 -#define PORTCON_PORTC_OD_C0_MASK (((1U << PORTCON_PORTC_OD_C0_WIDTH) - 1U) << PORTCON_PORTC_OD_C0_SHIFT) -#define PORTCON_PORTC_OD_C0_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C0_BITS_DISABLE (PORTCON_PORTC_OD_C0_VALUE_DISABLE << PORTCON_PORTC_OD_C0_SHIFT) -#define PORTCON_PORTC_OD_C0_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C0_BITS_ENABLE (PORTCON_PORTC_OD_C0_VALUE_ENABLE << PORTCON_PORTC_OD_C0_SHIFT) - -#define PORTCON_PORTC_OD_C1_SHIFT 1 -#define PORTCON_PORTC_OD_C1_WIDTH 1 -#define PORTCON_PORTC_OD_C1_MASK (((1U << PORTCON_PORTC_OD_C1_WIDTH) - 1U) << PORTCON_PORTC_OD_C1_SHIFT) -#define PORTCON_PORTC_OD_C1_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C1_BITS_DISABLE (PORTCON_PORTC_OD_C1_VALUE_DISABLE << PORTCON_PORTC_OD_C1_SHIFT) -#define PORTCON_PORTC_OD_C1_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C1_BITS_ENABLE (PORTCON_PORTC_OD_C1_VALUE_ENABLE << PORTCON_PORTC_OD_C1_SHIFT) - -#define PORTCON_PORTC_OD_C2_SHIFT 2 -#define PORTCON_PORTC_OD_C2_WIDTH 1 -#define PORTCON_PORTC_OD_C2_MASK (((1U << PORTCON_PORTC_OD_C2_WIDTH) - 1U) << PORTCON_PORTC_OD_C2_SHIFT) -#define PORTCON_PORTC_OD_C2_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C2_BITS_DISABLE (PORTCON_PORTC_OD_C2_VALUE_DISABLE << PORTCON_PORTC_OD_C2_SHIFT) -#define PORTCON_PORTC_OD_C2_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C2_BITS_ENABLE (PORTCON_PORTC_OD_C2_VALUE_ENABLE << PORTCON_PORTC_OD_C2_SHIFT) - -#define PORTCON_PORTC_OD_C3_SHIFT 3 -#define PORTCON_PORTC_OD_C3_WIDTH 1 -#define PORTCON_PORTC_OD_C3_MASK (((1U << PORTCON_PORTC_OD_C3_WIDTH) - 1U) << PORTCON_PORTC_OD_C3_SHIFT) -#define PORTCON_PORTC_OD_C3_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C3_BITS_DISABLE (PORTCON_PORTC_OD_C3_VALUE_DISABLE << PORTCON_PORTC_OD_C3_SHIFT) -#define PORTCON_PORTC_OD_C3_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C3_BITS_ENABLE (PORTCON_PORTC_OD_C3_VALUE_ENABLE << PORTCON_PORTC_OD_C3_SHIFT) - -#define PORTCON_PORTC_OD_C4_SHIFT 4 -#define PORTCON_PORTC_OD_C4_WIDTH 1 -#define PORTCON_PORTC_OD_C4_MASK (((1U << PORTCON_PORTC_OD_C4_WIDTH) - 1U) << PORTCON_PORTC_OD_C4_SHIFT) -#define PORTCON_PORTC_OD_C4_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C4_BITS_DISABLE (PORTCON_PORTC_OD_C4_VALUE_DISABLE << PORTCON_PORTC_OD_C4_SHIFT) -#define PORTCON_PORTC_OD_C4_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C4_BITS_ENABLE (PORTCON_PORTC_OD_C4_VALUE_ENABLE << PORTCON_PORTC_OD_C4_SHIFT) - -#define PORTCON_PORTC_OD_C5_SHIFT 5 -#define PORTCON_PORTC_OD_C5_WIDTH 1 -#define PORTCON_PORTC_OD_C5_MASK (((1U << PORTCON_PORTC_OD_C5_WIDTH) - 1U) << PORTCON_PORTC_OD_C5_SHIFT) -#define PORTCON_PORTC_OD_C5_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C5_BITS_DISABLE (PORTCON_PORTC_OD_C5_VALUE_DISABLE << PORTCON_PORTC_OD_C5_SHIFT) -#define PORTCON_PORTC_OD_C5_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C5_BITS_ENABLE (PORTCON_PORTC_OD_C5_VALUE_ENABLE << PORTCON_PORTC_OD_C5_SHIFT) - -#define PORTCON_PORTC_OD_C6_SHIFT 6 -#define PORTCON_PORTC_OD_C6_WIDTH 1 -#define PORTCON_PORTC_OD_C6_MASK (((1U << PORTCON_PORTC_OD_C6_WIDTH) - 1U) << PORTCON_PORTC_OD_C6_SHIFT) -#define PORTCON_PORTC_OD_C6_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C6_BITS_DISABLE (PORTCON_PORTC_OD_C6_VALUE_DISABLE << PORTCON_PORTC_OD_C6_SHIFT) -#define PORTCON_PORTC_OD_C6_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C6_BITS_ENABLE (PORTCON_PORTC_OD_C6_VALUE_ENABLE << PORTCON_PORTC_OD_C6_SHIFT) - -#define PORTCON_PORTC_OD_C7_SHIFT 7 -#define PORTCON_PORTC_OD_C7_WIDTH 1 -#define PORTCON_PORTC_OD_C7_MASK (((1U << PORTCON_PORTC_OD_C7_WIDTH) - 1U) << PORTCON_PORTC_OD_C7_SHIFT) -#define PORTCON_PORTC_OD_C7_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C7_BITS_DISABLE (PORTCON_PORTC_OD_C7_VALUE_DISABLE << PORTCON_PORTC_OD_C7_SHIFT) -#define PORTCON_PORTC_OD_C7_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C7_BITS_ENABLE (PORTCON_PORTC_OD_C7_VALUE_ENABLE << PORTCON_PORTC_OD_C7_SHIFT) - -#define PORTCON_PORTC_OD_C8_SHIFT 8 -#define PORTCON_PORTC_OD_C8_WIDTH 1 -#define PORTCON_PORTC_OD_C8_MASK (((1U << PORTCON_PORTC_OD_C8_WIDTH) - 1U) << PORTCON_PORTC_OD_C8_SHIFT) -#define PORTCON_PORTC_OD_C8_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C8_BITS_DISABLE (PORTCON_PORTC_OD_C8_VALUE_DISABLE << PORTCON_PORTC_OD_C8_SHIFT) -#define PORTCON_PORTC_OD_C8_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C8_BITS_ENABLE (PORTCON_PORTC_OD_C8_VALUE_ENABLE << PORTCON_PORTC_OD_C8_SHIFT) - -#define PORTCON_PORTC_OD_C9_SHIFT 9 -#define PORTCON_PORTC_OD_C9_WIDTH 1 -#define PORTCON_PORTC_OD_C9_MASK (((1U << PORTCON_PORTC_OD_C9_WIDTH) - 1U) << PORTCON_PORTC_OD_C9_SHIFT) -#define PORTCON_PORTC_OD_C9_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C9_BITS_DISABLE (PORTCON_PORTC_OD_C9_VALUE_DISABLE << PORTCON_PORTC_OD_C9_SHIFT) -#define PORTCON_PORTC_OD_C9_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C9_BITS_ENABLE (PORTCON_PORTC_OD_C9_VALUE_ENABLE << PORTCON_PORTC_OD_C9_SHIFT) - -#define PORTCON_PORTC_OD_C10_SHIFT 10 -#define PORTCON_PORTC_OD_C10_WIDTH 1 -#define PORTCON_PORTC_OD_C10_MASK (((1U << PORTCON_PORTC_OD_C10_WIDTH) - 1U) << PORTCON_PORTC_OD_C10_SHIFT) -#define PORTCON_PORTC_OD_C10_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C10_BITS_DISABLE (PORTCON_PORTC_OD_C10_VALUE_DISABLE << PORTCON_PORTC_OD_C10_SHIFT) -#define PORTCON_PORTC_OD_C10_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C10_BITS_ENABLE (PORTCON_PORTC_OD_C10_VALUE_ENABLE << PORTCON_PORTC_OD_C10_SHIFT) - -#define PORTCON_PORTC_OD_C11_SHIFT 11 -#define PORTCON_PORTC_OD_C11_WIDTH 1 -#define PORTCON_PORTC_OD_C11_MASK (((1U << PORTCON_PORTC_OD_C11_WIDTH) - 1U) << PORTCON_PORTC_OD_C11_SHIFT) -#define PORTCON_PORTC_OD_C11_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C11_BITS_DISABLE (PORTCON_PORTC_OD_C11_VALUE_DISABLE << PORTCON_PORTC_OD_C11_SHIFT) -#define PORTCON_PORTC_OD_C11_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C11_BITS_ENABLE (PORTCON_PORTC_OD_C11_VALUE_ENABLE << PORTCON_PORTC_OD_C11_SHIFT) - -#define PORTCON_PORTC_OD_C12_SHIFT 12 -#define PORTCON_PORTC_OD_C12_WIDTH 1 -#define PORTCON_PORTC_OD_C12_MASK (((1U << PORTCON_PORTC_OD_C12_WIDTH) - 1U) << PORTCON_PORTC_OD_C12_SHIFT) -#define PORTCON_PORTC_OD_C12_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C12_BITS_DISABLE (PORTCON_PORTC_OD_C12_VALUE_DISABLE << PORTCON_PORTC_OD_C12_SHIFT) -#define PORTCON_PORTC_OD_C12_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C12_BITS_ENABLE (PORTCON_PORTC_OD_C12_VALUE_ENABLE << PORTCON_PORTC_OD_C12_SHIFT) - -#define PORTCON_PORTC_OD_C13_SHIFT 13 -#define PORTCON_PORTC_OD_C13_WIDTH 1 -#define PORTCON_PORTC_OD_C13_MASK (((1U << PORTCON_PORTC_OD_C13_WIDTH) - 1U) << PORTCON_PORTC_OD_C13_SHIFT) -#define PORTCON_PORTC_OD_C13_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C13_BITS_DISABLE (PORTCON_PORTC_OD_C13_VALUE_DISABLE << PORTCON_PORTC_OD_C13_SHIFT) -#define PORTCON_PORTC_OD_C13_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C13_BITS_ENABLE (PORTCON_PORTC_OD_C13_VALUE_ENABLE << PORTCON_PORTC_OD_C13_SHIFT) - -#define PORTCON_PORTC_OD_C14_SHIFT 14 -#define PORTCON_PORTC_OD_C14_WIDTH 1 -#define PORTCON_PORTC_OD_C14_MASK (((1U << PORTCON_PORTC_OD_C14_WIDTH) - 1U) << PORTCON_PORTC_OD_C14_SHIFT) -#define PORTCON_PORTC_OD_C14_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C14_BITS_DISABLE (PORTCON_PORTC_OD_C14_VALUE_DISABLE << PORTCON_PORTC_OD_C14_SHIFT) -#define PORTCON_PORTC_OD_C14_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C14_BITS_ENABLE (PORTCON_PORTC_OD_C14_VALUE_ENABLE << PORTCON_PORTC_OD_C14_SHIFT) - -#define PORTCON_PORTC_OD_C15_SHIFT 15 -#define PORTCON_PORTC_OD_C15_WIDTH 1 -#define PORTCON_PORTC_OD_C15_MASK (((1U << PORTCON_PORTC_OD_C15_WIDTH) - 1U) << PORTCON_PORTC_OD_C15_SHIFT) -#define PORTCON_PORTC_OD_C15_VALUE_DISABLE 0U -#define PORTCON_PORTC_OD_C15_BITS_DISABLE (PORTCON_PORTC_OD_C15_VALUE_DISABLE << PORTCON_PORTC_OD_C15_SHIFT) -#define PORTCON_PORTC_OD_C15_VALUE_ENABLE 1U -#define PORTCON_PORTC_OD_C15_BITS_ENABLE (PORTCON_PORTC_OD_C15_VALUE_ENABLE << PORTCON_PORTC_OD_C15_SHIFT) - - -#endif - diff --git a/App/bsp/dp32g030/pwmplus.h b/App/bsp/dp32g030/pwmplus.h deleted file mode 100644 index 3b744753..00000000 --- a/App/bsp/dp32g030/pwmplus.h +++ /dev/null @@ -1,146 +0,0 @@ -#ifndef HARDWARE_DP32G030_PWMPLUS_H -#define HARDWARE_DP32G030_PWMPLUS_H - -#define PWM_PLUS0_BASE_ADDR 0x400B4000U - -//--------------- - -#define PWMPLUS_CFG 0x00U - -#define PWMPLUS_CFG_COUNTER_EN_SHIFT 0U -#define PWMPLUS_CFG_COUNTER_EN_WIDTH 1U -#define PWMPLUS_CFG_COUNTER_EN_MASK (((1U << PWMPLUS_CFG_COUNTER_EN_WIDTH) - 1U) << PWMPLUS_CFG_COUNTER_EN_SHIFT) -#define PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE 1U -#define PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE (PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE << PWMPLUS_CFG_COUNTER_EN_SHIFT) - -#define PWMPLUS_CFG_CNT_TYPE_SHIFT 1U - -#define PWMPLUS_CFG_CNT_REP_SHIFT 2U -#define PWMPLUS_CFG_CNT_REP_WIDTH 1U -#define PWMPLUS_CFG_CNT_REP_VALUE_ENABLE 1U -#define PWMPLUS_CFG_CNT_REP_BITS_ENABLE (PWMPLUS_CFG_CNT_REP_VALUE_ENABLE << PWMPLUS_CFG_CNT_REP_SHIFT) - -#define PWMPLUS_CFG_OUT_MODE_SHIFT 3U -#define PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE 1U -#define PWMPLUS_CFG_OUT_MODE_BITS_ENABLE (PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE << PWMPLUS_CFG_OUT_MODE_SHIFT) - -#define PWMPLUS_CFG_AUTO_RELOAD_SHIFT 8U - -//--------------- - -#define PWMPLUS_GEN 0x04U - -#define PWMPLUS_GEN_CH0_OE_SHIFT 24U -#define PWMPLUS_GEN_CH0_OE_WIDTH 1U -#define PWMPLUS_GEN_CH0_OE_VALUE_ENABLE 1U -#define PWMPLUS_GEN_CH0_OE_BITS_ENABLE (PWMPLUS_GEN_CH0_OE_VALUE_ENABLE << PWMPLUS_GEN_CH0_OE_SHIFT) - -#define PWMPLUS_GEN_CH0_OUTINV_SHIFT 16U -#define PWMPLUS_GEN_CH0_OUTINV_WIDTH 1U -#define PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE 1U -#define PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE (PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE << PWMPLUS_GEN_CH0_OUTINV_SHIFT) - -#define PWMPLUS_GEN_CH0_START_SHIFT 8U -#define PWMPLUS_GEN_CH0_START_WIDTH 1U -#define PWMPLUS_GEN_CH0_START_VALUE_ENABLE 1U -#define PWMPLUS_GEN_CH0_START_BITS_ENABLE (PWMPLUS_GEN_CH0_START_VALUE_ENABLE << PWMPLUS_GEN_CH0_START_SHIFT) - -#define PWMPLUS_GEN_CH0_IDLE_SHIFT 0U -#define PWMPLUS_GEN_CH0_IDLE_WIDTH 1U -#define PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE 1U -#define PWMPLUS_GEN_CH0_IDLE_BITS_ENABLE (PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE << PWMPLUS_GEN_CH0_IDLE_SHIFT) - -//--------------- - -#define PWMPLUS_CLKSRC 0x08U -#define PWMPLUS_BRAKE_CFG 0x0CU -#define PWMPLUS_MASK_LEV 0x10U -#define PWMPLUS_PERIOD 0x1CU -#define PWMPLUS_CH0_COMP 0x20U -#define PWMPLUS_CH1_COMP 0x24U -#define PWMPLUS_CH2_COMP 0x28U -#define PWMPLUS_CH0_DT 0x30U -#define PWMPLUS_CH1_DT 0x34U -#define PWMPLUS_CH2_DT 0x38U -#define PWMPLUS_TRIG_COMP 0x40U -#define PWMPLUS_TRIG_CFG 0x44U -#define PWMPLUS_IE 0x60U -#define PWMPLUS_IF 0x64U -#define PWMPLUS_SWLOAD 0x84U -#define PWMPLUS_MASK_EN 0x88 -#define PWMPLUS_CNT_ST 0xE0 -#define PWMPLUS_BRAKE_ST 0xE4 - - - - - - - - - - - - - -#define PWM_PLUS0_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CFG) -#define PWM_PLUS0_CFG (*(volatile uint32_t *)PWM_PLUS0_CFG_ADDR) - -#define PWM_PLUS0_GEN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_GEN) -#define PWM_PLUS0_GEN (*(volatile uint32_t *)PWM_PLUS0_GEN_ADDR) - -#define PWM_PLUS0_CLKSRC_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CLKSRC) -#define PWM_PLUS0_CLKSRC (*(volatile uint32_t *)PWM_PLUS0_CLKSRC_ADDR) - -#define PWM_PLUS0_BRAKE_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_CFG) -#define PWM_PLUS0_BRAKE_CFG (*(volatile uint32_t *)PWM_PLUS0_BRAKE_CFG_ADDR) - -#define PWM_PLUS0_MASK_LEV_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_LEV) -#define PWM_PLUS0_MASK_LEV (*(volatile uint32_t *)PWM_PLUS0_MASK_LEV_ADDR) - -#define PWM_PLUS0_PERIOD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_PERIOD) -#define PWM_PLUS0_PERIOD (*(volatile uint32_t *)PWM_PLUS0_PERIOD_ADDR) - -#define PWM_PLUS0_CH0_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_COMP) -#define PWM_PLUS0_CH0_COMP (*(volatile uint32_t *)PWM_PLUS0_CH0_COMP_ADDR) - -#define PWM_PLUS0_CH1_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_COMP) -#define PWM_PLUS0_CH1_COMP (*(volatile uint32_t *)PWM_PLUS0_CH1_COMP_ADDR) - -#define PWM_PLUS0_CH2_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_COMP) -#define PWM_PLUS0_CH2_COMP (*(volatile uint32_t *)PWM_PLUS0_CH2_COMP_ADDR) - -#define PWM_PLUS0_CH0_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_DT) -#define PWM_PLUS0_CH0_DT (*(volatile uint32_t *)PWM_PLUS0_CH0_DT_ADDR) - -#define PWM_PLUS0_CH1_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_DT) -#define PWM_PLUS0_CH1_DT (*(volatile uint32_t *)PWM_PLUS0_CH1_DT_ADDR) - -#define PWM_PLUS0_CH2_DT_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_DT) -#define PWM_PLUS0_CH2_DT (*(volatile uint32_t *)PWM_PLUS0_CH2_DT_ADDR) - -#define PWM_PLUS0_TRIG_COMP_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_COMP) -#define PWM_PLUS0_TRIG_COMP (*(volatile uint32_t *)PWM_PLUS0_TRIG_COMP_ADDR) - -#define PWM_PLUS0_TRIG_CFG_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_CFG) -#define PWM_PLUS0_TRIG_CFG (*(volatile uint32_t *)PWM_PLUS0_TRIG_CFG_ADDR) - -#define PWM_PLUS0_IE_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IE) -#define PWM_PLUS0_IE (*(volatile uint32_t *)PWM_PLUS0_IE_ADDR) - -#define PWM_PLUS0_IF_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_IF) -#define PWM_PLUS0_IF (*(volatile uint32_t *)PWM_PLUS0_IF_ADDR) - -#define PWM_PLUS0_SWLOAD_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_SWLOAD) -#define PWM_PLUS0_SWLOAD (*(volatile uint32_t *)PWM_PLUS0_SWLOAD_ADDR) - -#define PWM_PLUS0_MASK_EN_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_EN) -#define PWM_PLUS0_MASK_EN (*(volatile uint32_t *)PWM_PLUS0_MASK_EN_ADDR) - -#define PWM_PLUS0_CNT_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_CNT_ST) -#define PWM_PLUS0_CNT_ST (*(volatile uint32_t *)PWM_PLUS0_CNT_ST_ADDR) - -#define PWM_PLUS0_BRAKE_ST_ADDR (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_ST) -#define PWM_PLUS0_BRAKE_ST (*(volatile uint32_t *)PWM_PLUS0_BRAKE_ST_ADDR) - -#endif \ No newline at end of file diff --git a/App/bsp/dp32g030/saradc.h b/App/bsp/dp32g030/saradc.h deleted file mode 100644 index 94761308..00000000 --- a/App/bsp/dp32g030/saradc.h +++ /dev/null @@ -1,253 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_SARADC_H -#define HARDWARE_DP32G030_SARADC_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- SARADC -------- */ -#define SARADC_BASE_ADDR 0x400BA000U -#define SARADC_BASE_SIZE 0x00000800U - -#define SARADC_CFG_ADDR (SARADC_BASE_ADDR + 0x0000U) -#define SARADC_CFG (*(volatile uint32_t *)SARADC_CFG_ADDR) -#define SARADC_CFG_CH_SEL_SHIFT 0 -#define SARADC_CFG_CH_SEL_WIDTH 15 -#define SARADC_CFG_CH_SEL_MASK (((1U << SARADC_CFG_CH_SEL_WIDTH) - 1U) << SARADC_CFG_CH_SEL_SHIFT) -#define SARADC_CFG_AVG_SHIFT 16 -#define SARADC_CFG_AVG_WIDTH 2 -#define SARADC_CFG_AVG_MASK (((1U << SARADC_CFG_AVG_WIDTH) - 1U) << SARADC_CFG_AVG_SHIFT) -#define SARADC_CFG_AVG_VALUE_1_SAMPLE 0U -#define SARADC_CFG_AVG_BITS_1_SAMPLE (SARADC_CFG_AVG_VALUE_1_SAMPLE << SARADC_CFG_AVG_SHIFT) -#define SARADC_CFG_AVG_VALUE_2_SAMPLE 1U -#define SARADC_CFG_AVG_BITS_2_SAMPLE (SARADC_CFG_AVG_VALUE_2_SAMPLE << SARADC_CFG_AVG_SHIFT) -#define SARADC_CFG_AVG_VALUE_4_SAMPLE 2U -#define SARADC_CFG_AVG_BITS_4_SAMPLE (SARADC_CFG_AVG_VALUE_4_SAMPLE << SARADC_CFG_AVG_SHIFT) -#define SARADC_CFG_AVG_VALUE_8_SAMPLE 3U -#define SARADC_CFG_AVG_BITS_8_SAMPLE (SARADC_CFG_AVG_VALUE_8_SAMPLE << SARADC_CFG_AVG_SHIFT) - -#define SARADC_CFG_CONT_SHIFT 18 -#define SARADC_CFG_CONT_WIDTH 1 -#define SARADC_CFG_CONT_MASK (((1U << SARADC_CFG_CONT_WIDTH) - 1U) << SARADC_CFG_CONT_SHIFT) -#define SARADC_CFG_CONT_VALUE_SINGLE 0U -#define SARADC_CFG_CONT_BITS_SINGLE (SARADC_CFG_CONT_VALUE_SINGLE << SARADC_CFG_CONT_SHIFT) -#define SARADC_CFG_CONT_VALUE_CONTINUOUS 1U -#define SARADC_CFG_CONT_BITS_CONTINUOUS (SARADC_CFG_CONT_VALUE_CONTINUOUS << SARADC_CFG_CONT_SHIFT) - -#define SARADC_CFG_SMPL_SETUP_SHIFT 19 -#define SARADC_CFG_SMPL_SETUP_WIDTH 3 -#define SARADC_CFG_SMPL_SETUP_MASK (((1U << SARADC_CFG_SMPL_SETUP_WIDTH) - 1U) << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE 0U -#define SARADC_CFG_SMPL_SETUP_BITS_1_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE 1U -#define SARADC_CFG_SMPL_SETUP_BITS_2_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE 2U -#define SARADC_CFG_SMPL_SETUP_BITS_4_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE 3U -#define SARADC_CFG_SMPL_SETUP_BITS_8_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE 4U -#define SARADC_CFG_SMPL_SETUP_BITS_16_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE 5U -#define SARADC_CFG_SMPL_SETUP_BITS_32_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE 6U -#define SARADC_CFG_SMPL_SETUP_BITS_64_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) -#define SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE 7U -#define SARADC_CFG_SMPL_SETUP_BITS_128_CYCLE (SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) - -#define SARADC_CFG_MEM_MODE_SHIFT 22 -#define SARADC_CFG_MEM_MODE_WIDTH 1 -#define SARADC_CFG_MEM_MODE_MASK (((1U << SARADC_CFG_MEM_MODE_WIDTH) - 1U) << SARADC_CFG_MEM_MODE_SHIFT) -#define SARADC_CFG_MEM_MODE_VALUE_FIFO 0U -#define SARADC_CFG_MEM_MODE_BITS_FIFO (SARADC_CFG_MEM_MODE_VALUE_FIFO << SARADC_CFG_MEM_MODE_SHIFT) -#define SARADC_CFG_MEM_MODE_VALUE_CHANNEL 1U -#define SARADC_CFG_MEM_MODE_BITS_CHANNEL (SARADC_CFG_MEM_MODE_VALUE_CHANNEL << SARADC_CFG_MEM_MODE_SHIFT) - -#define SARADC_CFG_SMPL_CLK_SHIFT 23 -#define SARADC_CFG_SMPL_CLK_WIDTH 1 -#define SARADC_CFG_SMPL_CLK_MASK (((1U << SARADC_CFG_SMPL_CLK_WIDTH) - 1U) << SARADC_CFG_SMPL_CLK_SHIFT) -#define SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL 0U -#define SARADC_CFG_SMPL_CLK_BITS_EXTERNAL (SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL << SARADC_CFG_SMPL_CLK_SHIFT) -#define SARADC_CFG_SMPL_CLK_VALUE_INTERNAL 1U -#define SARADC_CFG_SMPL_CLK_BITS_INTERNAL (SARADC_CFG_SMPL_CLK_VALUE_INTERNAL << SARADC_CFG_SMPL_CLK_SHIFT) - -#define SARADC_CFG_SMPL_WIN_SHIFT 24 -#define SARADC_CFG_SMPL_WIN_WIDTH 3 -#define SARADC_CFG_SMPL_WIN_MASK (((1U << SARADC_CFG_SMPL_WIN_WIDTH) - 1U) << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE 0U -#define SARADC_CFG_SMPL_WIN_BITS_1_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE 1U -#define SARADC_CFG_SMPL_WIN_BITS_3_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE 2U -#define SARADC_CFG_SMPL_WIN_BITS_5_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE 3U -#define SARADC_CFG_SMPL_WIN_BITS_7_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE 4U -#define SARADC_CFG_SMPL_WIN_BITS_9_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE 5U -#define SARADC_CFG_SMPL_WIN_BITS_11_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE 6U -#define SARADC_CFG_SMPL_WIN_BITS_13_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) -#define SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE 7U -#define SARADC_CFG_SMPL_WIN_BITS_15_CYCLE (SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) - -#define SARADC_CFG_ADC_EN_SHIFT 27 -#define SARADC_CFG_ADC_EN_WIDTH 1 -#define SARADC_CFG_ADC_EN_MASK (((1U << SARADC_CFG_ADC_EN_WIDTH) - 1U) << SARADC_CFG_ADC_EN_SHIFT) -#define SARADC_CFG_ADC_EN_VALUE_DISABLE 0U -#define SARADC_CFG_ADC_EN_BITS_DISABLE (SARADC_CFG_ADC_EN_VALUE_DISABLE << SARADC_CFG_ADC_EN_SHIFT) -#define SARADC_CFG_ADC_EN_VALUE_ENABLE 1U -#define SARADC_CFG_ADC_EN_BITS_ENABLE (SARADC_CFG_ADC_EN_VALUE_ENABLE << SARADC_CFG_ADC_EN_SHIFT) - -#define SARADC_CFG_ADC_TRIG_SHIFT 28 -#define SARADC_CFG_ADC_TRIG_WIDTH 1 -#define SARADC_CFG_ADC_TRIG_MASK (((1U << SARADC_CFG_ADC_TRIG_WIDTH) - 1U) << SARADC_CFG_ADC_TRIG_SHIFT) -#define SARADC_CFG_ADC_TRIG_VALUE_CPU 0U -#define SARADC_CFG_ADC_TRIG_BITS_CPU (SARADC_CFG_ADC_TRIG_VALUE_CPU << SARADC_CFG_ADC_TRIG_SHIFT) -#define SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL 1U -#define SARADC_CFG_ADC_TRIG_BITS_EXTERNAL (SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL << SARADC_CFG_ADC_TRIG_SHIFT) - -#define SARADC_CFG_DMA_EN_SHIFT 29 -#define SARADC_CFG_DMA_EN_WIDTH 1 -#define SARADC_CFG_DMA_EN_MASK (((1U << SARADC_CFG_DMA_EN_WIDTH) - 1U) << SARADC_CFG_DMA_EN_SHIFT) -#define SARADC_CFG_DMA_EN_VALUE_DISABLE 0U -#define SARADC_CFG_DMA_EN_BITS_DISABLE (SARADC_CFG_DMA_EN_VALUE_DISABLE << SARADC_CFG_DMA_EN_SHIFT) -#define SARADC_CFG_DMA_EN_VALUE_ENABLE 1U -#define SARADC_CFG_DMA_EN_BITS_ENABLE (SARADC_CFG_DMA_EN_VALUE_ENABLE << SARADC_CFG_DMA_EN_SHIFT) - -#define SARADC_START_ADDR (SARADC_BASE_ADDR + 0x0004U) -#define SARADC_START (*(volatile uint32_t *)SARADC_START_ADDR) -#define SARADC_START_START_SHIFT 0 -#define SARADC_START_START_WIDTH 1 -#define SARADC_START_START_MASK (((1U << SARADC_START_START_WIDTH) - 1U) << SARADC_START_START_SHIFT) -#define SARADC_START_START_VALUE_DISABLE 0U -#define SARADC_START_START_BITS_DISABLE (SARADC_START_START_VALUE_DISABLE << SARADC_START_START_SHIFT) -#define SARADC_START_START_VALUE_ENABLE 1U -#define SARADC_START_START_BITS_ENABLE (SARADC_START_START_VALUE_ENABLE << SARADC_START_START_SHIFT) - -#define SARADC_START_SOFT_RESET_SHIFT 2 -#define SARADC_START_SOFT_RESET_WIDTH 1 -#define SARADC_START_SOFT_RESET_MASK (((1U << SARADC_START_SOFT_RESET_WIDTH) - 1U) << SARADC_START_SOFT_RESET_SHIFT) -#define SARADC_START_SOFT_RESET_VALUE_ASSERT 0U -#define SARADC_START_SOFT_RESET_BITS_ASSERT (SARADC_START_SOFT_RESET_VALUE_ASSERT << SARADC_START_SOFT_RESET_SHIFT) -#define SARADC_START_SOFT_RESET_VALUE_DEASSERT 1U -#define SARADC_START_SOFT_RESET_BITS_DEASSERT (SARADC_START_SOFT_RESET_VALUE_DEASSERT << SARADC_START_SOFT_RESET_SHIFT) - -#define SARADC_IE_ADDR (SARADC_BASE_ADDR + 0x0008U) -#define SARADC_IE (*(volatile uint32_t *)SARADC_IE_ADDR) -#define SARADC_IE_CHx_EOC_SHIFT 0 -#define SARADC_IE_CHx_EOC_WIDTH 16 -#define SARADC_IE_CHx_EOC_MASK (((1U << SARADC_IE_CHx_EOC_WIDTH) - 1U) << SARADC_IE_CHx_EOC_SHIFT) -#define SARADC_IE_CHx_EOC_VALUE_NONE 0U -#define SARADC_IE_CHx_EOC_BITS_NONE (SARADC_IE_CHx_EOC_VALUE_NONE << SARADC_IE_CHx_EOC_SHIFT) -#define SARADC_IE_CHx_EOC_VALUE_ALL 65535U -#define SARADC_IE_CHx_EOC_BITS_ALL (SARADC_IE_CHx_EOC_VALUE_ALL << SARADC_IE_CHx_EOC_SHIFT) - -#define SARADC_IE_FIFO_FULL_SHIFT 16 -#define SARADC_IE_FIFO_FULL_WIDTH 1 -#define SARADC_IE_FIFO_FULL_MASK (((1U << SARADC_IE_FIFO_FULL_WIDTH) - 1U) << SARADC_IE_FIFO_FULL_SHIFT) -#define SARADC_IE_FIFO_FULL_VALUE_DISABLE 0U -#define SARADC_IE_FIFO_FULL_BITS_DISABLE (SARADC_IE_FIFO_FULL_VALUE_DISABLE << SARADC_IE_FIFO_FULL_SHIFT) -#define SARADC_IE_FIFO_FULL_VALUE_ENABLE 1U -#define SARADC_IE_FIFO_FULL_BITS_ENABLE (SARADC_IE_FIFO_FULL_VALUE_ENABLE << SARADC_IE_FIFO_FULL_SHIFT) - -#define SARADC_IE_FIFO_HFULL_SHIFT 17 -#define SARADC_IE_FIFO_HFULL_WIDTH 1 -#define SARADC_IE_FIFO_HFULL_MASK (((1U << SARADC_IE_FIFO_HFULL_WIDTH) - 1U) << SARADC_IE_FIFO_HFULL_SHIFT) -#define SARADC_IE_FIFO_HFULL_VALUE_DISABLE 0U -#define SARADC_IE_FIFO_HFULL_BITS_DISABLE (SARADC_IE_FIFO_HFULL_VALUE_DISABLE << SARADC_IE_FIFO_HFULL_SHIFT) -#define SARADC_IE_FIFO_HFULL_VALUE_ENABLE 1U -#define SARADC_IE_FIFO_HFULL_BITS_ENABLE (SARADC_IE_FIFO_HFULL_VALUE_ENABLE << SARADC_IE_FIFO_HFULL_SHIFT) - -#define SARADC_IF_ADDR (SARADC_BASE_ADDR + 0x000CU) -#define SARADC_IF (*(volatile uint32_t *)SARADC_IF_ADDR) -#define SARADC_IF_CHx_EOC_SHIFT 0 -#define SARADC_IF_CHx_EOC_WIDTH 16 -#define SARADC_IF_CHx_EOC_MASK (((1U << SARADC_IF_CHx_EOC_WIDTH) - 1U) << SARADC_IF_CHx_EOC_SHIFT) -#define SARADC_IF_FIFO_FULL_SHIFT 16 -#define SARADC_IF_FIFO_FULL_WIDTH 1 -#define SARADC_IF_FIFO_FULL_MASK (((1U << SARADC_IF_FIFO_FULL_WIDTH) - 1U) << SARADC_IF_FIFO_FULL_SHIFT) -#define SARADC_IF_FIFO_FULL_VALUE_NOT_SET 0U -#define SARADC_IF_FIFO_FULL_BITS_NOT_SET (SARADC_IF_FIFO_FULL_VALUE_NOT_SET << SARADC_IF_FIFO_FULL_SHIFT) -#define SARADC_IF_FIFO_FULL_VALUE_SET 1U -#define SARADC_IF_FIFO_FULL_BITS_SET (SARADC_IF_FIFO_FULL_VALUE_SET << SARADC_IF_FIFO_FULL_SHIFT) - -#define SARADC_IF_FIFO_HFULL_SHIFT 17 -#define SARADC_IF_FIFO_HFULL_WIDTH 1 -#define SARADC_IF_FIFO_HFULL_MASK (((1U << SARADC_IF_FIFO_HFULL_WIDTH) - 1U) << SARADC_IF_FIFO_HFULL_SHIFT) -#define SARADC_IF_FIFO_HFULL_VALUE_NOT_SET 0U -#define SARADC_IF_FIFO_HFULL_BITS_NOT_SET (SARADC_IF_FIFO_HFULL_VALUE_NOT_SET << SARADC_IF_FIFO_HFULL_SHIFT) -#define SARADC_IF_FIFO_HFULL_VALUE_SET 1U -#define SARADC_IF_FIFO_HFULL_BITS_SET (SARADC_IF_FIFO_HFULL_VALUE_SET << SARADC_IF_FIFO_HFULL_SHIFT) - -#define SARADC_CH0_ADDR (SARADC_BASE_ADDR + 0x0010U) -#define SARADC_CH0 (*(volatile uint32_t *)SARADC_CH0_ADDR) -#define SARADC_EXTTRIG_SEL_ADDR (SARADC_BASE_ADDR + 0x00B0U) -#define SARADC_EXTTRIG_SEL (*(volatile uint32_t *)SARADC_EXTTRIG_SEL_ADDR) - -#define SARADC_CALIB_OFFSET_ADDR (SARADC_BASE_ADDR + 0x00F0U) -#define SARADC_CALIB_OFFSET (*(volatile uint32_t *)SARADC_CALIB_OFFSET_ADDR) -#define SARADC_CALIB_OFFSET_OFFSET_SHIFT 0 -#define SARADC_CALIB_OFFSET_OFFSET_WIDTH 8 -#define SARADC_CALIB_OFFSET_OFFSET_MASK (((1U << SARADC_CALIB_OFFSET_OFFSET_WIDTH) - 1U) << SARADC_CALIB_OFFSET_OFFSET_SHIFT) -#define SARADC_CALIB_OFFSET_VALID_SHIFT 16 -#define SARADC_CALIB_OFFSET_VALID_WIDTH 1 -#define SARADC_CALIB_OFFSET_VALID_MASK (((1U << SARADC_CALIB_OFFSET_VALID_WIDTH) - 1U) << SARADC_CALIB_OFFSET_VALID_SHIFT) -#define SARADC_CALIB_OFFSET_VALID_VALUE_NO 0U -#define SARADC_CALIB_OFFSET_VALID_BITS_NO (SARADC_CALIB_OFFSET_VALID_VALUE_NO << SARADC_CALIB_OFFSET_VALID_SHIFT) -#define SARADC_CALIB_OFFSET_VALID_VALUE_YES 1U -#define SARADC_CALIB_OFFSET_VALID_BITS_YES (SARADC_CALIB_OFFSET_VALID_VALUE_YES << SARADC_CALIB_OFFSET_VALID_SHIFT) - -#define SARADC_CALIB_KD_ADDR (SARADC_BASE_ADDR + 0x00F4U) -#define SARADC_CALIB_KD (*(volatile uint32_t *)SARADC_CALIB_KD_ADDR) -#define SARADC_CALIB_KD_KD_SHIFT 0 -#define SARADC_CALIB_KD_KD_WIDTH 8 -#define SARADC_CALIB_KD_KD_MASK (((1U << SARADC_CALIB_KD_KD_WIDTH) - 1U) << SARADC_CALIB_KD_KD_SHIFT) -#define SARADC_CALIB_KD_VALID_SHIFT 16 -#define SARADC_CALIB_KD_VALID_WIDTH 1 -#define SARADC_CALIB_KD_VALID_MASK (((1U << SARADC_CALIB_KD_VALID_WIDTH) - 1U) << SARADC_CALIB_KD_VALID_SHIFT) -#define SARADC_CALIB_KD_VALID_VALUE_NO 0U -#define SARADC_CALIB_KD_VALID_BITS_NO (SARADC_CALIB_KD_VALID_VALUE_NO << SARADC_CALIB_KD_VALID_SHIFT) -#define SARADC_CALIB_KD_VALID_VALUE_YES 1U -#define SARADC_CALIB_KD_VALID_BITS_YES (SARADC_CALIB_KD_VALID_VALUE_YES << SARADC_CALIB_KD_VALID_SHIFT) - -/* -------- ADC_CHx -------- */ - -typedef struct { - uint32_t STAT; - uint32_t DATA; -} ADC_Channel_t; - -#define ADC_CHx_STAT_EOC_SHIFT 0 -#define ADC_CHx_STAT_EOC_WIDTH 1 -#define ADC_CHx_STAT_EOC_MASK (((1U << ADC_CHx_STAT_EOC_WIDTH) - 1U) << ADC_CHx_STAT_EOC_SHIFT) -#define ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE 0U -#define ADC_CHx_STAT_EOC_BITS_NOT_COMPLETE (ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE << ADC_CHx_STAT_EOC_SHIFT) -#define ADC_CHx_STAT_EOC_VALUE_COMPLETE 1U -#define ADC_CHx_STAT_EOC_BITS_COMPLETE (ADC_CHx_STAT_EOC_VALUE_COMPLETE << ADC_CHx_STAT_EOC_SHIFT) - -#define ADC_CHx_DATA_DATA_SHIFT 0 -#define ADC_CHx_DATA_DATA_WIDTH 12 -#define ADC_CHx_DATA_DATA_MASK (((1U << ADC_CHx_DATA_DATA_WIDTH) - 1U) << ADC_CHx_DATA_DATA_SHIFT) -#define ADC_CHx_DATA_NUM_SHIFT 12 -#define ADC_CHx_DATA_NUM_WIDTH 4 -#define ADC_CHx_DATA_NUM_MASK (((1U << ADC_CHx_DATA_NUM_WIDTH) - 1U) << ADC_CHx_DATA_NUM_SHIFT) - - -#endif - diff --git a/App/bsp/dp32g030/spi.h b/App/bsp/dp32g030/spi.h deleted file mode 100644 index a8e744f7..00000000 --- a/App/bsp/dp32g030/spi.h +++ /dev/null @@ -1,240 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_SPI_H -#define HARDWARE_DP32G030_SPI_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- SPI0 -------- */ -#define SPI0_BASE_ADDR 0x400B8000U -#define SPI0_BASE_SIZE 0x00000800U -#define SPI0 ((volatile SPI_Port_t *)SPI0_BASE_ADDR) - -/* -------- SPI1 -------- */ -#define SPI1_BASE_ADDR 0x400B8800U -#define SPI1_BASE_SIZE 0x00000800U -#define SPI1 ((volatile SPI_Port_t *)SPI1_BASE_ADDR) - -/* -------- SPI -------- */ - -typedef struct { - uint32_t CR; - uint32_t WDR; - uint32_t RDR; - uint32_t Reserved_000C[1]; - uint32_t IE; - uint32_t IF; - uint32_t FIFOST; -} SPI_Port_t; - -#define SPI_CR_SPR_SHIFT 0 -#define SPI_CR_SPR_WIDTH 3 -#define SPI_CR_SPR_MASK (((1U << SPI_CR_SPR_WIDTH) - 1U) << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_4 0U -#define SPI_CR_SPR_BITS_FPCLK_DIV_4 (SPI_CR_SPR_VALUE_FPCLK_DIV_4 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_8 1U -#define SPI_CR_SPR_BITS_FPCLK_DIV_8 (SPI_CR_SPR_VALUE_FPCLK_DIV_8 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_16 2U -#define SPI_CR_SPR_BITS_FPCLK_DIV_16 (SPI_CR_SPR_VALUE_FPCLK_DIV_16 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_32 3U -#define SPI_CR_SPR_BITS_FPCLK_DIV_32 (SPI_CR_SPR_VALUE_FPCLK_DIV_32 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_64 4U -#define SPI_CR_SPR_BITS_FPCLK_DIV_64 (SPI_CR_SPR_VALUE_FPCLK_DIV_64 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_128 5U -#define SPI_CR_SPR_BITS_FPCLK_DIV_128 (SPI_CR_SPR_VALUE_FPCLK_DIV_128 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_256 6U -#define SPI_CR_SPR_BITS_FPCLK_DIV_256 (SPI_CR_SPR_VALUE_FPCLK_DIV_256 << SPI_CR_SPR_SHIFT) -#define SPI_CR_SPR_VALUE_FPCLK_DIV_512 7U -#define SPI_CR_SPR_BITS_FPCLK_DIV_512 (SPI_CR_SPR_VALUE_FPCLK_DIV_512 << SPI_CR_SPR_SHIFT) - -#define SPI_CR_SPE_SHIFT 3 -#define SPI_CR_SPE_WIDTH 1 -#define SPI_CR_SPE_MASK (((1U << SPI_CR_SPE_WIDTH) - 1U) << SPI_CR_SPE_SHIFT) -#define SPI_CR_SPE_VALUE_DISABLE 0U -#define SPI_CR_SPE_BITS_DISABLE (SPI_CR_SPE_VALUE_DISABLE << SPI_CR_SPE_SHIFT) -#define SPI_CR_SPE_VALUE_ENABLE 1U -#define SPI_CR_SPE_BITS_ENABLE (SPI_CR_SPE_VALUE_ENABLE << SPI_CR_SPE_SHIFT) - -#define SPI_CR_CPHA_SHIFT 4 -#define SPI_CR_CPHA_WIDTH 1 -#define SPI_CR_CPHA_MASK (((1U << SPI_CR_CPHA_WIDTH) - 1U) << SPI_CR_CPHA_SHIFT) -#define SPI_CR_CPOL_SHIFT 5 -#define SPI_CR_CPOL_WIDTH 1 -#define SPI_CR_CPOL_MASK (((1U << SPI_CR_CPOL_WIDTH) - 1U) << SPI_CR_CPOL_SHIFT) -#define SPI_CR_MSTR_SHIFT 6 -#define SPI_CR_MSTR_WIDTH 1 -#define SPI_CR_MSTR_MASK (((1U << SPI_CR_MSTR_WIDTH) - 1U) << SPI_CR_MSTR_SHIFT) -#define SPI_CR_LSB_SHIFT 7 -#define SPI_CR_LSB_WIDTH 1 -#define SPI_CR_LSB_MASK (((1U << SPI_CR_LSB_WIDTH) - 1U) << SPI_CR_LSB_SHIFT) -#define SPI_CR_CPHA_DATA_HOLD_S_SHIFT 8 -#define SPI_CR_CPHA_DATA_HOLD_S_WIDTH 4 -#define SPI_CR_CPHA_DATA_HOLD_S_MASK (((1U << SPI_CR_CPHA_DATA_HOLD_S_WIDTH) - 1U) << SPI_CR_CPHA_DATA_HOLD_S_SHIFT) -#define SPI_CR_MSR_SSN_SHIFT 12 -#define SPI_CR_MSR_SSN_WIDTH 1 -#define SPI_CR_MSR_SSN_MASK (((1U << SPI_CR_MSR_SSN_WIDTH) - 1U) << SPI_CR_MSR_SSN_SHIFT) -#define SPI_CR_MSR_SSN_VALUE_DISABLE 0U -#define SPI_CR_MSR_SSN_BITS_DISABLE (SPI_CR_MSR_SSN_VALUE_DISABLE << SPI_CR_MSR_SSN_SHIFT) -#define SPI_CR_MSR_SSN_VALUE_ENABLE 1U -#define SPI_CR_MSR_SSN_BITS_ENABLE (SPI_CR_MSR_SSN_VALUE_ENABLE << SPI_CR_MSR_SSN_SHIFT) - -#define SPI_CR_RXDMAEN_SHIFT 13 -#define SPI_CR_RXDMAEN_WIDTH 1 -#define SPI_CR_RXDMAEN_MASK (((1U << SPI_CR_RXDMAEN_WIDTH) - 1U) << SPI_CR_RXDMAEN_SHIFT) -#define SPI_CR_TXDMAEN_SHIFT 14 -#define SPI_CR_TXDMAEN_WIDTH 1 -#define SPI_CR_TXDMAEN_MASK (((1U << SPI_CR_TXDMAEN_WIDTH) - 1U) << SPI_CR_TXDMAEN_SHIFT) -#define SPI_CR_RF_CLR_SHIFT 15 -#define SPI_CR_RF_CLR_WIDTH 1 -#define SPI_CR_RF_CLR_MASK (((1U << SPI_CR_RF_CLR_WIDTH) - 1U) << SPI_CR_RF_CLR_SHIFT) -#define SPI_CR_TF_CLR_SHIFT 16 -#define SPI_CR_TF_CLR_WIDTH 1 -#define SPI_CR_TF_CLR_MASK (((1U << SPI_CR_TF_CLR_WIDTH) - 1U) << SPI_CR_TF_CLR_SHIFT) - -#define SPI_IE_RXFIFO_OVF_SHIFT 0 -#define SPI_IE_RXFIFO_OVF_WIDTH 1 -#define SPI_IE_RXFIFO_OVF_MASK (((1U << SPI_IE_RXFIFO_OVF_WIDTH) - 1U) << SPI_IE_RXFIFO_OVF_SHIFT) -#define SPI_IE_RXFIFO_OVF_VALUE_DISABLE 0U -#define SPI_IE_RXFIFO_OVF_BITS_DISABLE (SPI_IE_RXFIFO_OVF_VALUE_DISABLE << SPI_IE_RXFIFO_OVF_SHIFT) -#define SPI_IE_RXFIFO_OVF_VALUE_ENABLE 1U -#define SPI_IE_RXFIFO_OVF_BITS_ENABLE (SPI_IE_RXFIFO_OVF_VALUE_ENABLE << SPI_IE_RXFIFO_OVF_SHIFT) - -#define SPI_IE_RXFIFO_FULL_SHIFT 1 -#define SPI_IE_RXFIFO_FULL_WIDTH 1 -#define SPI_IE_RXFIFO_FULL_MASK (((1U << SPI_IE_RXFIFO_FULL_WIDTH) - 1U) << SPI_IE_RXFIFO_FULL_SHIFT) -#define SPI_IE_RXFIFO_FULL_VALUE_DISABLE 0U -#define SPI_IE_RXFIFO_FULL_BITS_DISABLE (SPI_IE_RXFIFO_FULL_VALUE_DISABLE << SPI_IE_RXFIFO_FULL_SHIFT) -#define SPI_IE_RXFIFO_FULL_VALUE_ENABLE 1U -#define SPI_IE_RXFIFO_FULL_BITS_ENABLE (SPI_IE_RXFIFO_FULL_VALUE_ENABLE << SPI_IE_RXFIFO_FULL_SHIFT) - -#define SPI_IE_RXFIFO_HFULL_SHIFT 2 -#define SPI_IE_RXFIFO_HFULL_WIDTH 1 -#define SPI_IE_RXFIFO_HFULL_MASK (((1U << SPI_IE_RXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_RXFIFO_HFULL_SHIFT) -#define SPI_IE_RXFIFO_HFULL_VALUE_DISABLE 0U -#define SPI_IE_RXFIFO_HFULL_BITS_DISABLE (SPI_IE_RXFIFO_HFULL_VALUE_DISABLE << SPI_IE_RXFIFO_HFULL_SHIFT) -#define SPI_IE_RXFIFO_HFULL_VALUE_ENABLE 1U -#define SPI_IE_RXFIFO_HFULL_BITS_ENABLE (SPI_IE_RXFIFO_HFULL_VALUE_ENABLE << SPI_IE_RXFIFO_HFULL_SHIFT) - -#define SPI_IE_TXFIFO_EMPTY_SHIFT 3 -#define SPI_IE_TXFIFO_EMPTY_WIDTH 1 -#define SPI_IE_TXFIFO_EMPTY_MASK (((1U << SPI_IE_TXFIFO_EMPTY_WIDTH) - 1U) << SPI_IE_TXFIFO_EMPTY_SHIFT) -#define SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE 0U -#define SPI_IE_TXFIFO_EMPTY_BITS_DISABLE (SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE << SPI_IE_TXFIFO_EMPTY_SHIFT) -#define SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE 1U -#define SPI_IE_TXFIFO_EMPTY_BITS_ENABLE (SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE << SPI_IE_TXFIFO_EMPTY_SHIFT) - -#define SPI_IE_TXFIFO_HFULL_SHIFT 4 -#define SPI_IE_TXFIFO_HFULL_WIDTH 1 -#define SPI_IE_TXFIFO_HFULL_MASK (((1U << SPI_IE_TXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_TXFIFO_HFULL_SHIFT) -#define SPI_IE_TXFIFO_HFULL_VALUE_DISABLE 0U -#define SPI_IE_TXFIFO_HFULL_BITS_DISABLE (SPI_IE_TXFIFO_HFULL_VALUE_DISABLE << SPI_IE_TXFIFO_HFULL_SHIFT) -#define SPI_IE_TXFIFO_HFULL_VALUE_ENABLE 1U -#define SPI_IE_TXFIFO_HFULL_BITS_ENABLE (SPI_IE_TXFIFO_HFULL_VALUE_ENABLE << SPI_IE_TXFIFO_HFULL_SHIFT) - -#define SPI_FIFOST_RFE_SHIFT 0 -#define SPI_FIFOST_RFE_WIDTH 1 -#define SPI_FIFOST_RFE_MASK (((1U << SPI_FIFOST_RFE_WIDTH) - 1U) << SPI_FIFOST_RFE_SHIFT) -#define SPI_FIFOST_RFE_VALUE_NOT_EMPTY 0U -#define SPI_FIFOST_RFE_BITS_NOT_EMPTY (SPI_FIFOST_RFE_VALUE_NOT_EMPTY << SPI_FIFOST_RFE_SHIFT) -#define SPI_FIFOST_RFE_VALUE_EMPTY 1U -#define SPI_FIFOST_RFE_BITS_EMPTY (SPI_FIFOST_RFE_VALUE_EMPTY << SPI_FIFOST_RFE_SHIFT) - -#define SPI_FIFOST_RFF_SHIFT 1 -#define SPI_FIFOST_RFF_WIDTH 1 -#define SPI_FIFOST_RFF_MASK (((1U << SPI_FIFOST_RFF_WIDTH) - 1U) << SPI_FIFOST_RFF_SHIFT) -#define SPI_FIFOST_RFF_VALUE_NOT_FULL 0U -#define SPI_FIFOST_RFF_BITS_NOT_FULL (SPI_FIFOST_RFF_VALUE_NOT_FULL << SPI_FIFOST_RFF_SHIFT) -#define SPI_FIFOST_RFF_VALUE_FULL 1U -#define SPI_FIFOST_RFF_BITS_FULL (SPI_FIFOST_RFF_VALUE_FULL << SPI_FIFOST_RFF_SHIFT) - -#define SPI_FIFOST_RFHF_SHIFT 2 -#define SPI_FIFOST_RFHF_WIDTH 1 -#define SPI_FIFOST_RFHF_MASK (((1U << SPI_FIFOST_RFHF_WIDTH) - 1U) << SPI_FIFOST_RFHF_SHIFT) -#define SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL 0U -#define SPI_FIFOST_RFHF_BITS_NOT_HALF_FULL (SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_RFHF_SHIFT) -#define SPI_FIFOST_RFHF_VALUE_HALF_FULL 1U -#define SPI_FIFOST_RFHF_BITS_HALF_FULL (SPI_FIFOST_RFHF_VALUE_HALF_FULL << SPI_FIFOST_RFHF_SHIFT) - -#define SPI_FIFOST_TFE_SHIFT 3 -#define SPI_FIFOST_TFE_WIDTH 1 -#define SPI_FIFOST_TFE_MASK (((1U << SPI_FIFOST_TFE_WIDTH) - 1U) << SPI_FIFOST_TFE_SHIFT) -#define SPI_FIFOST_TFE_VALUE_NOT_EMPTY 0U -#define SPI_FIFOST_TFE_BITS_NOT_EMPTY (SPI_FIFOST_TFE_VALUE_NOT_EMPTY << SPI_FIFOST_TFE_SHIFT) -#define SPI_FIFOST_TFE_VALUE_EMPTY 1U -#define SPI_FIFOST_TFE_BITS_EMPTY (SPI_FIFOST_TFE_VALUE_EMPTY << SPI_FIFOST_TFE_SHIFT) - -#define SPI_FIFOST_TFF_SHIFT 4 -#define SPI_FIFOST_TFF_WIDTH 1 -#define SPI_FIFOST_TFF_MASK (((1U << SPI_FIFOST_TFF_WIDTH) - 1U) << SPI_FIFOST_TFF_SHIFT) -#define SPI_FIFOST_TFF_VALUE_NOT_FULL 0U -#define SPI_FIFOST_TFF_BITS_NOT_FULL (SPI_FIFOST_TFF_VALUE_NOT_FULL << SPI_FIFOST_TFF_SHIFT) -#define SPI_FIFOST_TFF_VALUE_FULL 1U -#define SPI_FIFOST_TFF_BITS_FULL (SPI_FIFOST_TFF_VALUE_FULL << SPI_FIFOST_TFF_SHIFT) - -#define SPI_FIFOST_TFHF_SHIFT 5 -#define SPI_FIFOST_TFHF_WIDTH 1 -#define SPI_FIFOST_TFHF_MASK (((1U << SPI_FIFOST_TFHF_WIDTH) - 1U) << SPI_FIFOST_TFHF_SHIFT) -#define SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL 0U -#define SPI_FIFOST_TFHF_BITS_NOT_HALF_FULL (SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_TFHF_SHIFT) -#define SPI_FIFOST_TFHF_VALUE_HALF_FULL 1U -#define SPI_FIFOST_TFHF_BITS_HALF_FULL (SPI_FIFOST_TFHF_VALUE_HALF_FULL << SPI_FIFOST_TFHF_SHIFT) - -#define SPI_FIFOST_RF_LEVEL_SHIFT 6 -#define SPI_FIFOST_RF_LEVEL_WIDTH 3 -#define SPI_FIFOST_RF_LEVEL_MASK (((1U << SPI_FIFOST_RF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE 0U -#define SPI_FIFOST_RF_LEVEL_BITS_0_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE 1U -#define SPI_FIFOST_RF_LEVEL_BITS_1_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE 2U -#define SPI_FIFOST_RF_LEVEL_BITS_2_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE 3U -#define SPI_FIFOST_RF_LEVEL_BITS_3_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE 4U -#define SPI_FIFOST_RF_LEVEL_BITS_4_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE 5U -#define SPI_FIFOST_RF_LEVEL_BITS_5_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE 6U -#define SPI_FIFOST_RF_LEVEL_BITS_6_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) -#define SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE 7U -#define SPI_FIFOST_RF_LEVEL_BITS_7_BYTE (SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT) - -#define SPI_FIFOST_TF_LEVEL_SHIFT 9 -#define SPI_FIFOST_TF_LEVEL_WIDTH 3 -#define SPI_FIFOST_TF_LEVEL_MASK (((1U << SPI_FIFOST_TF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE 0U -#define SPI_FIFOST_TF_LEVEL_BITS_0_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE 1U -#define SPI_FIFOST_TF_LEVEL_BITS_1_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE 2U -#define SPI_FIFOST_TF_LEVEL_BITS_2_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE 3U -#define SPI_FIFOST_TF_LEVEL_BITS_3_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE 4U -#define SPI_FIFOST_TF_LEVEL_BITS_4_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE 5U -#define SPI_FIFOST_TF_LEVEL_BITS_5_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE 6U -#define SPI_FIFOST_TF_LEVEL_BITS_6_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) -#define SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE 7U -#define SPI_FIFOST_TF_LEVEL_BITS_7_BYTE (SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT) - - -#endif - diff --git a/App/bsp/dp32g030/syscon.h b/App/bsp/dp32g030/syscon.h deleted file mode 100644 index 92d638ab..00000000 --- a/App/bsp/dp32g030/syscon.h +++ /dev/null @@ -1,348 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_SYSCON_H -#define HARDWARE_DP32G030_SYSCON_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- SYSCON -------- */ -#define SYSCON_BASE_ADDR 0x40000000U -#define SYSCON_BASE_SIZE 0x00000800U - -#define SYSCON_CLK_SEL_ADDR (SYSCON_BASE_ADDR + 0x0000U) -#define SYSCON_CLK_SEL (*(volatile uint32_t *)SYSCON_CLK_SEL_ADDR) -#define SYSCON_CLK_SEL_SYS_SHIFT 0 -#define SYSCON_CLK_SEL_SYS_WIDTH 1 -#define SYSCON_CLK_SEL_SYS_MASK (((1U << SYSCON_CLK_SEL_SYS_WIDTH) - 1U) << SYSCON_CLK_SEL_SYS_SHIFT) -#define SYSCON_CLK_SEL_SYS_VALUE_RCHF 0U -#define SYSCON_CLK_SEL_SYS_BITS_RCHF (SYSCON_CLK_SEL_SYS_VALUE_RCHF << SYSCON_CLK_SEL_SYS_SHIFT) -#define SYSCON_CLK_SEL_SYS_VALUE_DIV_CLK 1U -#define SYSCON_CLK_SEL_SYS_BITS_DIV_CLK (SYSCON_CLK_SEL_SYS_VALUE_DIV_CLK << SYSCON_CLK_SEL_SYS_SHIFT) - -#define SYSCON_CLK_SEL_DIV_SHIFT 1 -#define SYSCON_CLK_SEL_DIV_WIDTH 3 -#define SYSCON_CLK_SEL_DIV_MASK (((1U << SYSCON_CLK_SEL_DIV_WIDTH) - 1U) << SYSCON_CLK_SEL_DIV_SHIFT) -#define SYSCON_CLK_SEL_DIV_VALUE_1 0U -#define SYSCON_CLK_SEL_DIV_BITS_1 (SYSCON_CLK_SEL_DIV_VALUE_1 << SYSCON_CLK_SEL_DIV_SHIFT) -#define SYSCON_CLK_SEL_DIV_VALUE_2 1U -#define SYSCON_CLK_SEL_DIV_BITS_2 (SYSCON_CLK_SEL_DIV_VALUE_2 << SYSCON_CLK_SEL_DIV_SHIFT) -#define SYSCON_CLK_SEL_DIV_VALUE_4 2U -#define SYSCON_CLK_SEL_DIV_BITS_4 (SYSCON_CLK_SEL_DIV_VALUE_4 << SYSCON_CLK_SEL_DIV_SHIFT) -#define SYSCON_CLK_SEL_DIV_VALUE_8 3U -#define SYSCON_CLK_SEL_DIV_BITS_8 (SYSCON_CLK_SEL_DIV_VALUE_8 << SYSCON_CLK_SEL_DIV_SHIFT) -#define SYSCON_CLK_SEL_DIV_VALUE_16 4U -#define SYSCON_CLK_SEL_DIV_BITS_16 (SYSCON_CLK_SEL_DIV_VALUE_16 << SYSCON_CLK_SEL_DIV_SHIFT) -#define SYSCON_CLK_SEL_DIV_VALUE_32 5U -#define SYSCON_CLK_SEL_DIV_BITS_32 (SYSCON_CLK_SEL_DIV_VALUE_32 << SYSCON_CLK_SEL_DIV_SHIFT) - -#define SYSCON_CLK_SEL_SRC_SHIFT 4 -#define SYSCON_CLK_SEL_SRC_WIDTH 3 -#define SYSCON_CLK_SEL_SRC_MASK (((1U << SYSCON_CLK_SEL_SRC_WIDTH) - 1U) << SYSCON_CLK_SEL_SRC_SHIFT) -#define SYSCON_CLK_SEL_SRC_VALUE_RCHF 0U -#define SYSCON_CLK_SEL_SRC_BITS_RCHF (SYSCON_CLK_SEL_SRC_VALUE_RCHF << SYSCON_CLK_SEL_SRC_SHIFT) -#define SYSCON_CLK_SEL_SRC_VALUE_RCLF 1U -#define SYSCON_CLK_SEL_SRC_BITS_RCLF (SYSCON_CLK_SEL_SRC_VALUE_RCLF << SYSCON_CLK_SEL_SRC_SHIFT) -#define SYSCON_CLK_SEL_SRC_VALUE_XTAH 2U -#define SYSCON_CLK_SEL_SRC_BITS_XTAH (SYSCON_CLK_SEL_SRC_VALUE_XTAH << SYSCON_CLK_SEL_SRC_SHIFT) -#define SYSCON_CLK_SEL_SRC_VALUE_XTAL 3U -#define SYSCON_CLK_SEL_SRC_BITS_XTAL (SYSCON_CLK_SEL_SRC_VALUE_XTAL << SYSCON_CLK_SEL_SRC_SHIFT) -#define SYSCON_CLK_SEL_SRC_VALUE_PLL 4U -#define SYSCON_CLK_SEL_SRC_BITS_PLL (SYSCON_CLK_SEL_SRC_VALUE_PLL << SYSCON_CLK_SEL_SRC_SHIFT) - -#define SYSCON_CLK_SEL_W_PLL_SHIFT 7 -#define SYSCON_CLK_SEL_W_PLL_WIDTH 1 -#define SYSCON_CLK_SEL_W_PLL_MASK (((1U << SYSCON_CLK_SEL_W_PLL_WIDTH) - 1U) << SYSCON_CLK_SEL_W_PLL_SHIFT) -#define SYSCON_CLK_SEL_W_PLL_VALUE_RCHF 0U -#define SYSCON_CLK_SEL_W_PLL_BITS_RCHF (SYSCON_CLK_SEL_W_PLL_VALUE_RCHF << SYSCON_CLK_SEL_W_PLL_SHIFT) -#define SYSCON_CLK_SEL_W_PLL_VALUE_XTAH 1U -#define SYSCON_CLK_SEL_W_PLL_BITS_XTAH (SYSCON_CLK_SEL_W_PLL_VALUE_XTAH << SYSCON_CLK_SEL_W_PLL_SHIFT) - -#define SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT 9 -#define SYSCON_CLK_SEL_R_SARADC_SMPL_WIDTH 2 -#define SYSCON_CLK_SEL_R_SARADC_SMPL_MASK (((1U << SYSCON_CLK_SEL_R_SARADC_SMPL_WIDTH) - 1U) << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV1 0U -#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV1 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV1 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV2 1U -#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV2 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV4 2U -#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV4 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV4 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV8 3U -#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV8 (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV8 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT) - -#define SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT 10 -#define SYSCON_CLK_SEL_W_SARADC_SMPL_WIDTH 2 -#define SYSCON_CLK_SEL_W_SARADC_SMPL_MASK (((1U << SYSCON_CLK_SEL_W_SARADC_SMPL_WIDTH) - 1U) << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV1 0U -#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV1 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV1 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2 1U -#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV2 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV4 2U -#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV4 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV4 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) -#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV8 3U -#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV8 (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV8 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) - -#define SYSCON_CLK_SEL_R_PLL_SHIFT 11 -#define SYSCON_CLK_SEL_R_PLL_WIDTH 1 -#define SYSCON_CLK_SEL_R_PLL_MASK (((1U << SYSCON_CLK_SEL_R_PLL_WIDTH) - 1U) << SYSCON_CLK_SEL_R_PLL_SHIFT) -#define SYSCON_CLK_SEL_R_PLL_VALUE_RCHF 0U -#define SYSCON_CLK_SEL_R_PLL_BITS_RCHF (SYSCON_CLK_SEL_R_PLL_VALUE_RCHF << SYSCON_CLK_SEL_R_PLL_SHIFT) -#define SYSCON_CLK_SEL_R_PLL_VALUE_XTAH 1U -#define SYSCON_CLK_SEL_R_PLL_BITS_XTAH (SYSCON_CLK_SEL_R_PLL_VALUE_XTAH << SYSCON_CLK_SEL_R_PLL_SHIFT) - -#define SYSCON_DIV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0004U) -#define SYSCON_DIV_CLK_GATE (*(volatile uint32_t *)SYSCON_DIV_CLK_GATE_ADDR) -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT 0 -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH 1 -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK (((1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH) - 1U) << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE 0U -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE 1U -#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_ENABLE (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT) - -#define SYSCON_DEV_CLK_GATE_ADDR (SYSCON_BASE_ADDR + 0x0008U) -#define SYSCON_DEV_CLK_GATE (*(volatile uint32_t *)SYSCON_DEV_CLK_GATE_ADDR) -#define SYSCON_DEV_CLK_GATE_GPIOA_SHIFT 0 -#define SYSCON_DEV_CLK_GATE_GPIOA_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_GPIOA_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOA_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_GPIOA_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_GPIOA_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT) - -#define SYSCON_DEV_CLK_GATE_GPIOB_SHIFT 1 -#define SYSCON_DEV_CLK_GATE_GPIOB_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_GPIOB_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOB_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_GPIOB_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_GPIOB_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT) - -#define SYSCON_DEV_CLK_GATE_GPIOC_SHIFT 2 -#define SYSCON_DEV_CLK_GATE_GPIOC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_GPIOC_MASK (((1U << SYSCON_DEV_CLK_GATE_GPIOC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_GPIOC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) -#define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_GPIOC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT) - -#define SYSCON_DEV_CLK_GATE_IIC0_SHIFT 4 -#define SYSCON_DEV_CLK_GATE_IIC0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_IIC0_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_IIC0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_IIC0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT) - -#define SYSCON_DEV_CLK_GATE_IIC1_SHIFT 5 -#define SYSCON_DEV_CLK_GATE_IIC1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_IIC1_MASK (((1U << SYSCON_DEV_CLK_GATE_IIC1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_IIC1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) -#define SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_IIC1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT) - -#define SYSCON_DEV_CLK_GATE_UART0_SHIFT 6 -#define SYSCON_DEV_CLK_GATE_UART0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_UART0_MASK (((1U << SYSCON_DEV_CLK_GATE_UART0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART0_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_UART0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_UART0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT) - -#define SYSCON_DEV_CLK_GATE_UART1_SHIFT 7 -#define SYSCON_DEV_CLK_GATE_UART1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_UART1_MASK (((1U << SYSCON_DEV_CLK_GATE_UART1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART1_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_UART1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_UART1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT) - -#define SYSCON_DEV_CLK_GATE_UART2_SHIFT 8 -#define SYSCON_DEV_CLK_GATE_UART2_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_UART2_MASK (((1U << SYSCON_DEV_CLK_GATE_UART2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART2_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_UART2_BITS_DISABLE (SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT) -#define SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_UART2_BITS_ENABLE (SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT) - -#define SYSCON_DEV_CLK_GATE_SPI0_SHIFT 10 -#define SYSCON_DEV_CLK_GATE_SPI0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_SPI0_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_SPI0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT) - -#define SYSCON_DEV_CLK_GATE_SPI1_SHIFT 11 -#define SYSCON_DEV_CLK_GATE_SPI1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_SPI1_MASK (((1U << SYSCON_DEV_CLK_GATE_SPI1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_SPI1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) -#define SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT) - -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT 12 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT) - -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT 13 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT) - -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT 14 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT) - -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT 15 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT) - -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT 16 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT) - -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT 17 -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT) - -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT 18 -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT) - -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT 20 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT) - -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT 21 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_MASK (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_DISABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_ENABLE (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT) - -#define SYSCON_DEV_CLK_GATE_RTC_SHIFT 22 -#define SYSCON_DEV_CLK_GATE_RTC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_RTC_MASK (((1U << SYSCON_DEV_CLK_GATE_RTC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_RTC_SHIFT) -#define SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_RTC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT) -#define SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_RTC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT) - -#define SYSCON_DEV_CLK_GATE_IWDT_SHIFT 23 -#define SYSCON_DEV_CLK_GATE_IWDT_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_IWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_IWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_IWDT_BITS_DISABLE (SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_IWDT_BITS_ENABLE (SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT) - -#define SYSCON_DEV_CLK_GATE_WWDT_SHIFT 24 -#define SYSCON_DEV_CLK_GATE_WWDT_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_WWDT_MASK (((1U << SYSCON_DEV_CLK_GATE_WWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_WWDT_BITS_DISABLE (SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) -#define SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_WWDT_BITS_ENABLE (SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT) - -#define SYSCON_DEV_CLK_GATE_SARADC_SHIFT 25 -#define SYSCON_DEV_CLK_GATE_SARADC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_SARADC_MASK (((1U << SYSCON_DEV_CLK_GATE_SARADC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) -#define SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_SARADC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) -#define SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT) - -#define SYSCON_DEV_CLK_GATE_CRC_SHIFT 27 -#define SYSCON_DEV_CLK_GATE_CRC_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_CRC_MASK (((1U << SYSCON_DEV_CLK_GATE_CRC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_CRC_SHIFT) -#define SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_CRC_BITS_DISABLE (SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT) -#define SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_CRC_BITS_ENABLE (SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT) - -#define SYSCON_DEV_CLK_GATE_AES_SHIFT 28 -#define SYSCON_DEV_CLK_GATE_AES_WIDTH 1 -#define SYSCON_DEV_CLK_GATE_AES_MASK (((1U << SYSCON_DEV_CLK_GATE_AES_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_AES_SHIFT) -#define SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE 0U -#define SYSCON_DEV_CLK_GATE_AES_BITS_DISABLE (SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT) -#define SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE 1U -#define SYSCON_DEV_CLK_GATE_AES_BITS_ENABLE (SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT) - -#define SYSCON_RC_FREQ_DELTA_ADDR (SYSCON_BASE_ADDR + 0x0078U) -#define SYSCON_RC_FREQ_DELTA (*(volatile uint32_t *)SYSCON_RC_FREQ_DELTA_ADDR) -#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT 0 -#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH 10 -#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT) -#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT 10 -#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH 1 -#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT) -#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT 11 -#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH 20 -#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT) -#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT 31 -#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH 1 -#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK (((1U << SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT) - -#define SYSCON_VREF_VOLT_DELTA_ADDR (SYSCON_BASE_ADDR + 0x007CU) -#define SYSCON_VREF_VOLT_DELTA (*(volatile uint32_t *)SYSCON_VREF_VOLT_DELTA_ADDR) -#define SYSCON_CHIP_ID0_ADDR (SYSCON_BASE_ADDR + 0x0080U) -#define SYSCON_CHIP_ID0 (*(volatile uint32_t *)SYSCON_CHIP_ID0_ADDR) -#define SYSCON_CHIP_ID1_ADDR (SYSCON_BASE_ADDR + 0x0084U) -#define SYSCON_CHIP_ID1 (*(volatile uint32_t *)SYSCON_CHIP_ID1_ADDR) -#define SYSCON_CHIP_ID2_ADDR (SYSCON_BASE_ADDR + 0x0088U) -#define SYSCON_CHIP_ID2 (*(volatile uint32_t *)SYSCON_CHIP_ID2_ADDR) -#define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU) -#define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR) - - -#endif - diff --git a/App/bsp/dp32g030/uart.h b/App/bsp/dp32g030/uart.h deleted file mode 100644 index f233eea7..00000000 --- a/App/bsp/dp32g030/uart.h +++ /dev/null @@ -1,439 +0,0 @@ -/* Copyright 2023 Dual Tachyon - * https://github.com/DualTachyon - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef HARDWARE_DP32G030_UART_H -#define HARDWARE_DP32G030_UART_H - -#if !defined(__ASSEMBLY__) -#include -#endif - -/* -------- UART0 -------- */ -#define UART0_BASE_ADDR 0x4006B000U -#define UART0_BASE_SIZE 0x00000800U -#define UART0 ((volatile UART_Port_t *)UART0_BASE_ADDR) - -/* -------- UART1 -------- */ -#define UART1_BASE_ADDR 0x4006B800U -#define UART1_BASE_SIZE 0x00000800U -#define UART1 ((volatile UART_Port_t *)UART1_BASE_ADDR) - -/* -------- UART2 -------- */ -#define UART2_BASE_ADDR 0x4006C000U -#define UART2_BASE_SIZE 0x00000800U -#define UART2 ((volatile UART_Port_t *)UART2_BASE_ADDR) - -/* -------- UART -------- */ - -typedef struct { - uint32_t CTRL; - uint32_t BAUD; - uint32_t TDR; - uint32_t RDR; - uint32_t IE; - uint32_t IF; - uint32_t FIFO; - uint32_t FC; - uint32_t RXTO; -} UART_Port_t; - -#define UART_CTRL_UARTEN_SHIFT 0 -#define UART_CTRL_UARTEN_WIDTH 1 -#define UART_CTRL_UARTEN_MASK (((1U << UART_CTRL_UARTEN_WIDTH) - 1U) << UART_CTRL_UARTEN_SHIFT) -#define UART_CTRL_UARTEN_VALUE_DISABLE 0U -#define UART_CTRL_UARTEN_BITS_DISABLE (UART_CTRL_UARTEN_VALUE_DISABLE << UART_CTRL_UARTEN_SHIFT) -#define UART_CTRL_UARTEN_VALUE_ENABLE 1U -#define UART_CTRL_UARTEN_BITS_ENABLE (UART_CTRL_UARTEN_VALUE_ENABLE << UART_CTRL_UARTEN_SHIFT) - -#define UART_CTRL_RXEN_SHIFT 1 -#define UART_CTRL_RXEN_WIDTH 1 -#define UART_CTRL_RXEN_MASK (((1U << UART_CTRL_RXEN_WIDTH) - 1U) << UART_CTRL_RXEN_SHIFT) -#define UART_CTRL_RXEN_VALUE_DISABLE 0U -#define UART_CTRL_RXEN_BITS_DISABLE (UART_CTRL_RXEN_VALUE_DISABLE << UART_CTRL_RXEN_SHIFT) -#define UART_CTRL_RXEN_VALUE_ENABLE 1U -#define UART_CTRL_RXEN_BITS_ENABLE (UART_CTRL_RXEN_VALUE_ENABLE << UART_CTRL_RXEN_SHIFT) - -#define UART_CTRL_TXEN_SHIFT 2 -#define UART_CTRL_TXEN_WIDTH 1 -#define UART_CTRL_TXEN_MASK (((1U << UART_CTRL_TXEN_WIDTH) - 1U) << UART_CTRL_TXEN_SHIFT) -#define UART_CTRL_TXEN_VALUE_DISABLE 0U -#define UART_CTRL_TXEN_BITS_DISABLE (UART_CTRL_TXEN_VALUE_DISABLE << UART_CTRL_TXEN_SHIFT) -#define UART_CTRL_TXEN_VALUE_ENABLE 1U -#define UART_CTRL_TXEN_BITS_ENABLE (UART_CTRL_TXEN_VALUE_ENABLE << UART_CTRL_TXEN_SHIFT) - -#define UART_CTRL_RXDMAEN_SHIFT 3 -#define UART_CTRL_RXDMAEN_WIDTH 1 -#define UART_CTRL_RXDMAEN_MASK (((1U << UART_CTRL_RXDMAEN_WIDTH) - 1U) << UART_CTRL_RXDMAEN_SHIFT) -#define UART_CTRL_RXDMAEN_VALUE_DISABLE 0U -#define UART_CTRL_RXDMAEN_BITS_DISABLE (UART_CTRL_RXDMAEN_VALUE_DISABLE << UART_CTRL_RXDMAEN_SHIFT) -#define UART_CTRL_RXDMAEN_VALUE_ENABLE 1U -#define UART_CTRL_RXDMAEN_BITS_ENABLE (UART_CTRL_RXDMAEN_VALUE_ENABLE << UART_CTRL_RXDMAEN_SHIFT) - -#define UART_CTRL_TXDMAEN_SHIFT 4 -#define UART_CTRL_TXDMAEN_WIDTH 1 -#define UART_CTRL_TXDMAEN_MASK (((1U << UART_CTRL_TXDMAEN_WIDTH) - 1U) << UART_CTRL_TXDMAEN_SHIFT) -#define UART_CTRL_TXDMAEN_VALUE_DISABLE 0U -#define UART_CTRL_TXDMAEN_BITS_DISABLE (UART_CTRL_TXDMAEN_VALUE_DISABLE << UART_CTRL_TXDMAEN_SHIFT) -#define UART_CTRL_TXDMAEN_VALUE_ENABLE 1U -#define UART_CTRL_TXDMAEN_BITS_ENABLE (UART_CTRL_TXDMAEN_VALUE_ENABLE << UART_CTRL_TXDMAEN_SHIFT) - -#define UART_CTRL_NINEBIT_SHIFT 5 -#define UART_CTRL_NINEBIT_WIDTH 1 -#define UART_CTRL_NINEBIT_MASK (((1U << UART_CTRL_NINEBIT_WIDTH) - 1U) << UART_CTRL_NINEBIT_SHIFT) -#define UART_CTRL_NINEBIT_VALUE_DISABLE 0U -#define UART_CTRL_NINEBIT_BITS_DISABLE (UART_CTRL_NINEBIT_VALUE_DISABLE << UART_CTRL_NINEBIT_SHIFT) -#define UART_CTRL_NINEBIT_VALUE_ENABLE 1U -#define UART_CTRL_NINEBIT_BITS_ENABLE (UART_CTRL_NINEBIT_VALUE_ENABLE << UART_CTRL_NINEBIT_SHIFT) - -#define UART_CTRL_PAREN_SHIFT 6 -#define UART_CTRL_PAREN_WIDTH 1 -#define UART_CTRL_PAREN_MASK (((1U << UART_CTRL_PAREN_WIDTH) - 1U) << UART_CTRL_PAREN_SHIFT) -#define UART_CTRL_PAREN_VALUE_DISABLE 0U -#define UART_CTRL_PAREN_BITS_DISABLE (UART_CTRL_PAREN_VALUE_DISABLE << UART_CTRL_PAREN_SHIFT) -#define UART_CTRL_PAREN_VALUE_ENABLE 1U -#define UART_CTRL_PAREN_BITS_ENABLE (UART_CTRL_PAREN_VALUE_ENABLE << UART_CTRL_PAREN_SHIFT) - -#define UART_IE_TXDONE_SHIFT 2 -#define UART_IE_TXDONE_WIDTH 1 -#define UART_IE_TXDONE_MASK (((1U << UART_IE_TXDONE_WIDTH) - 1U) << UART_IE_TXDONE_SHIFT) -#define UART_IE_TXDONE_VALUE_DISABLE 0U -#define UART_IE_TXDONE_BITS_DISABLE (UART_IE_TXDONE_VALUE_DISABLE << UART_IE_TXDONE_SHIFT) -#define UART_IE_TXDONE_VALUE_ENABLE 1U -#define UART_IE_TXDONE_BITS_ENABLE (UART_IE_TXDONE_VALUE_ENABLE << UART_IE_TXDONE_SHIFT) - -#define UART_IE_PARITYE_SHIFT 3 -#define UART_IE_PARITYE_WIDTH 1 -#define UART_IE_PARITYE_MASK (((1U << UART_IE_PARITYE_WIDTH) - 1U) << UART_IE_PARITYE_SHIFT) -#define UART_IE_PARITYE_VALUE_DISABLE 0U -#define UART_IE_PARITYE_BITS_DISABLE (UART_IE_PARITYE_VALUE_DISABLE << UART_IE_PARITYE_SHIFT) -#define UART_IE_PARITYE_VALUE_ENABLE 1U -#define UART_IE_PARITYE_BITS_ENABLE (UART_IE_PARITYE_VALUE_ENABLE << UART_IE_PARITYE_SHIFT) - -#define UART_IE_STOPE_SHIFT 4 -#define UART_IE_STOPE_WIDTH 1 -#define UART_IE_STOPE_MASK (((1U << UART_IE_STOPE_WIDTH) - 1U) << UART_IE_STOPE_SHIFT) -#define UART_IE_STOPE_VALUE_DISABLE 0U -#define UART_IE_STOPE_BITS_DISABLE (UART_IE_STOPE_VALUE_DISABLE << UART_IE_STOPE_SHIFT) -#define UART_IE_STOPE_VALUE_ENABLE 1U -#define UART_IE_STOPE_BITS_ENABLE (UART_IE_STOPE_VALUE_ENABLE << UART_IE_STOPE_SHIFT) - -#define UART_IE_RXTO_SHIFT 5 -#define UART_IE_RXTO_WIDTH 1 -#define UART_IE_RXTO_MASK (((1U << UART_IE_RXTO_WIDTH) - 1U) << UART_IE_RXTO_SHIFT) -#define UART_IE_RXTO_VALUE_DISABLE 0U -#define UART_IE_RXTO_BITS_DISABLE (UART_IE_RXTO_VALUE_DISABLE << UART_IE_RXTO_SHIFT) -#define UART_IE_RXTO_VALUE_ENABLE 1U -#define UART_IE_RXTO_BITS_ENABLE (UART_IE_RXTO_VALUE_ENABLE << UART_IE_RXTO_SHIFT) - -#define UART_IE_RXFIFO_SHIFT 6 -#define UART_IE_RXFIFO_WIDTH 1 -#define UART_IE_RXFIFO_MASK (((1U << UART_IE_RXFIFO_WIDTH) - 1U) << UART_IE_RXFIFO_SHIFT) -#define UART_IE_RXFIFO_VALUE_DISABLE 0U -#define UART_IE_RXFIFO_BITS_DISABLE (UART_IE_RXFIFO_VALUE_DISABLE << UART_IE_RXFIFO_SHIFT) -#define UART_IE_RXFIFO_VALUE_ENABLE 1U -#define UART_IE_RXFIFO_BITS_ENABLE (UART_IE_RXFIFO_VALUE_ENABLE << UART_IE_RXFIFO_SHIFT) - -#define UART_IE_TXFIFO_SHIFT 7 -#define UART_IE_TXFIFO_WIDTH 1 -#define UART_IE_TXFIFO_MASK (((1U << UART_IE_TXFIFO_WIDTH) - 1U) << UART_IE_TXFIFO_SHIFT) -#define UART_IE_TXFIFO_VALUE_DISABLE 0U -#define UART_IE_TXFIFO_BITS_DISABLE (UART_IE_TXFIFO_VALUE_DISABLE << UART_IE_TXFIFO_SHIFT) -#define UART_IE_TXFIFO_VALUE_ENABLE 1U -#define UART_IE_TXFIFO_BITS_ENABLE (UART_IE_TXFIFO_VALUE_ENABLE << UART_IE_TXFIFO_SHIFT) - -#define UART_IE_RXFIFO_OVF_SHIFT 8 -#define UART_IE_RXFIFO_OVF_WIDTH 1 -#define UART_IE_RXFIFO_OVF_MASK (((1U << UART_IE_RXFIFO_OVF_WIDTH) - 1U) << UART_IE_RXFIFO_OVF_SHIFT) -#define UART_IE_RXFIFO_OVF_VALUE_DISABLE 0U -#define UART_IE_RXFIFO_OVF_BITS_DISABLE (UART_IE_RXFIFO_OVF_VALUE_DISABLE << UART_IE_RXFIFO_OVF_SHIFT) -#define UART_IE_RXFIFO_OVF_VALUE_ENABLE 1U -#define UART_IE_RXFIFO_OVF_BITS_ENABLE (UART_IE_RXFIFO_OVF_VALUE_ENABLE << UART_IE_RXFIFO_OVF_SHIFT) - -#define UART_IE_ABRD_OVF_SHIFT 9 -#define UART_IE_ABRD_OVF_WIDTH 1 -#define UART_IE_ABRD_OVF_MASK (((1U << UART_IE_ABRD_OVF_WIDTH) - 1U) << UART_IE_ABRD_OVF_SHIFT) -#define UART_IE_ABRD_OVF_VALUE_DISABLE 0U -#define UART_IE_ABRD_OVF_BITS_DISABLE (UART_IE_ABRD_OVF_VALUE_DISABLE << UART_IE_ABRD_OVF_SHIFT) -#define UART_IE_ABRD_OVF_VALUE_ENABLE 1U -#define UART_IE_ABRD_OVF_BITS_ENABLE (UART_IE_ABRD_OVF_VALUE_ENABLE << UART_IE_ABRD_OVF_SHIFT) - -#define UART_IF_TXDONE_SHIFT 2 -#define UART_IF_TXDONE_WIDTH 1 -#define UART_IF_TXDONE_MASK (((1U << UART_IF_TXDONE_WIDTH) - 1U) << UART_IF_TXDONE_SHIFT) -#define UART_IF_TXDONE_VALUE_NOT_SET 0U -#define UART_IF_TXDONE_BITS_NOT_SET (UART_IF_TXDONE_VALUE_NOT_SET << UART_IF_TXDONE_SHIFT) -#define UART_IF_TXDONE_VALUE_SET 1U -#define UART_IF_TXDONE_BITS_SET (UART_IF_TXDONE_VALUE_SET << UART_IF_TXDONE_SHIFT) - -#define UART_IF_PARITYE_SHIFT 3 -#define UART_IF_PARITYE_WIDTH 1 -#define UART_IF_PARITYE_MASK (((1U << UART_IF_PARITYE_WIDTH) - 1U) << UART_IF_PARITYE_SHIFT) -#define UART_IF_PARITYE_VALUE_NOT_SET 0U -#define UART_IF_PARITYE_BITS_NOT_SET (UART_IF_PARITYE_VALUE_NOT_SET << UART_IF_PARITYE_SHIFT) -#define UART_IF_PARITYE_VALUE_SET 1U -#define UART_IF_PARITYE_BITS_SET (UART_IF_PARITYE_VALUE_SET << UART_IF_PARITYE_SHIFT) - -#define UART_IF_STOPE_SHIFT 4 -#define UART_IF_STOPE_WIDTH 1 -#define UART_IF_STOPE_MASK (((1U << UART_IF_STOPE_WIDTH) - 1U) << UART_IF_STOPE_SHIFT) -#define UART_IF_STOPE_VALUE_NOT_SET 0U -#define UART_IF_STOPE_BITS_NOT_SET (UART_IF_STOPE_VALUE_NOT_SET << UART_IF_STOPE_SHIFT) -#define UART_IF_STOPE_VALUE_SET 1U -#define UART_IF_STOPE_BITS_SET (UART_IF_STOPE_VALUE_SET << UART_IF_STOPE_SHIFT) - -#define UART_IF_RXTO_SHIFT 5 -#define UART_IF_RXTO_WIDTH 1 -#define UART_IF_RXTO_MASK (((1U << UART_IF_RXTO_WIDTH) - 1U) << UART_IF_RXTO_SHIFT) -#define UART_IF_RXTO_VALUE_NOT_SET 0U -#define UART_IF_RXTO_BITS_NOT_SET (UART_IF_RXTO_VALUE_NOT_SET << UART_IF_RXTO_SHIFT) -#define UART_IF_RXTO_VALUE_SET 1U -#define UART_IF_RXTO_BITS_SET (UART_IF_RXTO_VALUE_SET << UART_IF_RXTO_SHIFT) - -#define UART_IF_RXFIFO_SHIFT 6 -#define UART_IF_RXFIFO_WIDTH 1 -#define UART_IF_RXFIFO_MASK (((1U << UART_IF_RXFIFO_WIDTH) - 1U) << UART_IF_RXFIFO_SHIFT) -#define UART_IF_RXFIFO_VALUE_NOT_SET 0U -#define UART_IF_RXFIFO_BITS_NOT_SET (UART_IF_RXFIFO_VALUE_NOT_SET << UART_IF_RXFIFO_SHIFT) -#define UART_IF_RXFIFO_VALUE_SET 1U -#define UART_IF_RXFIFO_BITS_SET (UART_IF_RXFIFO_VALUE_SET << UART_IF_RXFIFO_SHIFT) - -#define UART_IF_TXFIFO_SHIFT 7 -#define UART_IF_TXFIFO_WIDTH 1 -#define UART_IF_TXFIFO_MASK (((1U << UART_IF_TXFIFO_WIDTH) - 1U) << UART_IF_TXFIFO_SHIFT) -#define UART_IF_TXFIFO_VALUE_NOT_SET 0U -#define UART_IF_TXFIFO_BITS_NOT_SET (UART_IF_TXFIFO_VALUE_NOT_SET << UART_IF_TXFIFO_SHIFT) -#define UART_IF_TXFIFO_VALUE_SET 1U -#define UART_IF_TXFIFO_BITS_SET (UART_IF_TXFIFO_VALUE_SET << UART_IF_TXFIFO_SHIFT) - -#define UART_IF_RXFIFO_OVF_SHIFT 8 -#define UART_IF_RXFIFO_OVF_WIDTH 1 -#define UART_IF_RXFIFO_OVF_MASK (((1U << UART_IF_RXFIFO_OVF_WIDTH) - 1U) << UART_IF_RXFIFO_OVF_SHIFT) -#define UART_IF_RXFIFO_OVF_VALUE_NOT_SET 0U -#define UART_IF_RXFIFO_OVF_BITS_NOT_SET (UART_IF_RXFIFO_OVF_VALUE_NOT_SET << UART_IF_RXFIFO_OVF_SHIFT) -#define UART_IF_RXFIFO_OVF_VALUE_SET 1U -#define UART_IF_RXFIFO_OVF_BITS_SET (UART_IF_RXFIFO_OVF_VALUE_SET << UART_IF_RXFIFO_OVF_SHIFT) - -#define UART_IF_ABRD_OVF_SHIFT 9 -#define UART_IF_ABRD_OVF_WIDTH 1 -#define UART_IF_ABRD_OVF_MASK (((1U << UART_IF_ABRD_OVF_WIDTH) - 1U) << UART_IF_ABRD_OVF_SHIFT) -#define UART_IF_ABRD_OVF_VALUE_NOT_SET 0U -#define UART_IF_ABRD_OVF_BITS_NOT_SET (UART_IF_ABRD_OVF_VALUE_NOT_SET << UART_IF_ABRD_OVF_SHIFT) -#define UART_IF_ABRD_OVF_VALUE_SET 1U -#define UART_IF_ABRD_OVF_BITS_SET (UART_IF_ABRD_OVF_VALUE_SET << UART_IF_ABRD_OVF_SHIFT) - -#define UART_IF_RXFIFO_EMPTY_SHIFT 10 -#define UART_IF_RXFIFO_EMPTY_WIDTH 1 -#define UART_IF_RXFIFO_EMPTY_MASK (((1U << UART_IF_RXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_RXFIFO_EMPTY_SHIFT) -#define UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET 0U -#define UART_IF_RXFIFO_EMPTY_BITS_NOT_SET (UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_RXFIFO_EMPTY_SHIFT) -#define UART_IF_RXFIFO_EMPTY_VALUE_SET 1U -#define UART_IF_RXFIFO_EMPTY_BITS_SET (UART_IF_RXFIFO_EMPTY_VALUE_SET << UART_IF_RXFIFO_EMPTY_SHIFT) - -#define UART_IF_RXFIFO_FULL_SHIFT 11 -#define UART_IF_RXFIFO_FULL_WIDTH 1 -#define UART_IF_RXFIFO_FULL_MASK (((1U << UART_IF_RXFIFO_FULL_WIDTH) - 1U) << UART_IF_RXFIFO_FULL_SHIFT) -#define UART_IF_RXFIFO_FULL_VALUE_NOT_SET 0U -#define UART_IF_RXFIFO_FULL_BITS_NOT_SET (UART_IF_RXFIFO_FULL_VALUE_NOT_SET << UART_IF_RXFIFO_FULL_SHIFT) -#define UART_IF_RXFIFO_FULL_VALUE_SET 1U -#define UART_IF_RXFIFO_FULL_BITS_SET (UART_IF_RXFIFO_FULL_VALUE_SET << UART_IF_RXFIFO_FULL_SHIFT) - -#define UART_IF_RXFIFO_HFULL_SHIFT 12 -#define UART_IF_RXFIFO_HFULL_WIDTH 1 -#define UART_IF_RXFIFO_HFULL_MASK (((1U << UART_IF_RXFIFO_HFULL_WIDTH) - 1U) << UART_IF_RXFIFO_HFULL_SHIFT) -#define UART_IF_RXFIFO_HFULL_VALUE_NOT_SET 0U -#define UART_IF_RXFIFO_HFULL_BITS_NOT_SET (UART_IF_RXFIFO_HFULL_VALUE_NOT_SET << UART_IF_RXFIFO_HFULL_SHIFT) -#define UART_IF_RXFIFO_HFULL_VALUE_SET 1U -#define UART_IF_RXFIFO_HFULL_BITS_SET (UART_IF_RXFIFO_HFULL_VALUE_SET << UART_IF_RXFIFO_HFULL_SHIFT) - -#define UART_IF_TXFIFO_EMPTY_SHIFT 13 -#define UART_IF_TXFIFO_EMPTY_WIDTH 1 -#define UART_IF_TXFIFO_EMPTY_MASK (((1U << UART_IF_TXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_TXFIFO_EMPTY_SHIFT) -#define UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET 0U -#define UART_IF_TXFIFO_EMPTY_BITS_NOT_SET (UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_TXFIFO_EMPTY_SHIFT) -#define UART_IF_TXFIFO_EMPTY_VALUE_SET 1U -#define UART_IF_TXFIFO_EMPTY_BITS_SET (UART_IF_TXFIFO_EMPTY_VALUE_SET << UART_IF_TXFIFO_EMPTY_SHIFT) - -#define UART_IF_TXFIFO_FULL_SHIFT 14 -#define UART_IF_TXFIFO_FULL_WIDTH 1 -#define UART_IF_TXFIFO_FULL_MASK (((1U << UART_IF_TXFIFO_FULL_WIDTH) - 1U) << UART_IF_TXFIFO_FULL_SHIFT) -#define UART_IF_TXFIFO_FULL_VALUE_NOT_SET 0U -#define UART_IF_TXFIFO_FULL_BITS_NOT_SET (UART_IF_TXFIFO_FULL_VALUE_NOT_SET << UART_IF_TXFIFO_FULL_SHIFT) -#define UART_IF_TXFIFO_FULL_VALUE_SET 1U -#define UART_IF_TXFIFO_FULL_BITS_SET (UART_IF_TXFIFO_FULL_VALUE_SET << UART_IF_TXFIFO_FULL_SHIFT) - -#define UART_IF_TXFIFO_HFULL_SHIFT 15 -#define UART_IF_TXFIFO_HFULL_WIDTH 1 -#define UART_IF_TXFIFO_HFULL_MASK (((1U << UART_IF_TXFIFO_HFULL_WIDTH) - 1U) << UART_IF_TXFIFO_HFULL_SHIFT) -#define UART_IF_TXFIFO_HFULL_VALUE_NOT_SET 0U -#define UART_IF_TXFIFO_HFULL_BITS_NOT_SET (UART_IF_TXFIFO_HFULL_VALUE_NOT_SET << UART_IF_TXFIFO_HFULL_SHIFT) -#define UART_IF_TXFIFO_HFULL_VALUE_SET 1U -#define UART_IF_TXFIFO_HFULL_BITS_SET (UART_IF_TXFIFO_HFULL_VALUE_SET << UART_IF_TXFIFO_HFULL_SHIFT) - -#define UART_IF_TXBUSY_SHIFT 16 -#define UART_IF_TXBUSY_WIDTH 1 -#define UART_IF_TXBUSY_MASK (((1U << UART_IF_TXBUSY_WIDTH) - 1U) << UART_IF_TXBUSY_SHIFT) -#define UART_IF_TXBUSY_VALUE_NOT_SET 0U -#define UART_IF_TXBUSY_BITS_NOT_SET (UART_IF_TXBUSY_VALUE_NOT_SET << UART_IF_TXBUSY_SHIFT) -#define UART_IF_TXBUSY_VALUE_SET 1U -#define UART_IF_TXBUSY_BITS_SET (UART_IF_TXBUSY_VALUE_SET << UART_IF_TXBUSY_SHIFT) - -#define UART_IF_RF_LEVEL_SHIFT 17 -#define UART_IF_RF_LEVEL_WIDTH 3 -#define UART_IF_RF_LEVEL_MASK (((1U << UART_IF_RF_LEVEL_WIDTH) - 1U) << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_0_8_BYTE 0U -#define UART_IF_RF_LEVEL_BITS_0_8_BYTE (UART_IF_RF_LEVEL_VALUE_0_8_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_1_BYTE 1U -#define UART_IF_RF_LEVEL_BITS_1_BYTE (UART_IF_RF_LEVEL_VALUE_1_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_2_BYTE 2U -#define UART_IF_RF_LEVEL_BITS_2_BYTE (UART_IF_RF_LEVEL_VALUE_2_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_3_BYTE 3U -#define UART_IF_RF_LEVEL_BITS_3_BYTE (UART_IF_RF_LEVEL_VALUE_3_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_4_BYTE 4U -#define UART_IF_RF_LEVEL_BITS_4_BYTE (UART_IF_RF_LEVEL_VALUE_4_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_5_BYTE 5U -#define UART_IF_RF_LEVEL_BITS_5_BYTE (UART_IF_RF_LEVEL_VALUE_5_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_6_BYTE 6U -#define UART_IF_RF_LEVEL_BITS_6_BYTE (UART_IF_RF_LEVEL_VALUE_6_BYTE << UART_IF_RF_LEVEL_SHIFT) -#define UART_IF_RF_LEVEL_VALUE_7_BYTE 7U -#define UART_IF_RF_LEVEL_BITS_7_BYTE (UART_IF_RF_LEVEL_VALUE_7_BYTE << UART_IF_RF_LEVEL_SHIFT) - -#define UART_IF_TF_LEVEL_SHIFT 20 -#define UART_IF_TF_LEVEL_WIDTH 3 -#define UART_IF_TF_LEVEL_MASK (((1U << UART_IF_TF_LEVEL_WIDTH) - 1U) << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_0_8_BYTE 0U -#define UART_IF_TF_LEVEL_BITS_0_8_BYTE (UART_IF_TF_LEVEL_VALUE_0_8_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_1_BYTE 1U -#define UART_IF_TF_LEVEL_BITS_1_BYTE (UART_IF_TF_LEVEL_VALUE_1_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_2_BYTE 2U -#define UART_IF_TF_LEVEL_BITS_2_BYTE (UART_IF_TF_LEVEL_VALUE_2_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_3_BYTE 3U -#define UART_IF_TF_LEVEL_BITS_3_BYTE (UART_IF_TF_LEVEL_VALUE_3_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_4_BYTE 4U -#define UART_IF_TF_LEVEL_BITS_4_BYTE (UART_IF_TF_LEVEL_VALUE_4_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_5_BYTE 5U -#define UART_IF_TF_LEVEL_BITS_5_BYTE (UART_IF_TF_LEVEL_VALUE_5_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_6_BYTE 6U -#define UART_IF_TF_LEVEL_BITS_6_BYTE (UART_IF_TF_LEVEL_VALUE_6_BYTE << UART_IF_TF_LEVEL_SHIFT) -#define UART_IF_TF_LEVEL_VALUE_7_BYTE 7U -#define UART_IF_TF_LEVEL_BITS_7_BYTE (UART_IF_TF_LEVEL_VALUE_7_BYTE << UART_IF_TF_LEVEL_SHIFT) - -#define UART_FIFO_RF_LEVEL_SHIFT 0 -#define UART_FIFO_RF_LEVEL_WIDTH 3 -#define UART_FIFO_RF_LEVEL_MASK (((1U << UART_FIFO_RF_LEVEL_WIDTH) - 1U) << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_1_BYTE 0U -#define UART_FIFO_RF_LEVEL_BITS_1_BYTE (UART_FIFO_RF_LEVEL_VALUE_1_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_2_BYTE 1U -#define UART_FIFO_RF_LEVEL_BITS_2_BYTE (UART_FIFO_RF_LEVEL_VALUE_2_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_3_BYTE 2U -#define UART_FIFO_RF_LEVEL_BITS_3_BYTE (UART_FIFO_RF_LEVEL_VALUE_3_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_4_BYTE 3U -#define UART_FIFO_RF_LEVEL_BITS_4_BYTE (UART_FIFO_RF_LEVEL_VALUE_4_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_5_BYTE 4U -#define UART_FIFO_RF_LEVEL_BITS_5_BYTE (UART_FIFO_RF_LEVEL_VALUE_5_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_6_BYTE 5U -#define UART_FIFO_RF_LEVEL_BITS_6_BYTE (UART_FIFO_RF_LEVEL_VALUE_6_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_7_BYTE 6U -#define UART_FIFO_RF_LEVEL_BITS_7_BYTE (UART_FIFO_RF_LEVEL_VALUE_7_BYTE << UART_FIFO_RF_LEVEL_SHIFT) -#define UART_FIFO_RF_LEVEL_VALUE_8_BYTE 7U -#define UART_FIFO_RF_LEVEL_BITS_8_BYTE (UART_FIFO_RF_LEVEL_VALUE_8_BYTE << UART_FIFO_RF_LEVEL_SHIFT) - -#define UART_FIFO_TF_LEVEL_SHIFT 3 -#define UART_FIFO_TF_LEVEL_WIDTH 3 -#define UART_FIFO_TF_LEVEL_MASK (((1U << UART_FIFO_TF_LEVEL_WIDTH) - 1U) << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_0_BYTE 0U -#define UART_FIFO_TF_LEVEL_BITS_0_BYTE (UART_FIFO_TF_LEVEL_VALUE_0_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_1_BYTE 1U -#define UART_FIFO_TF_LEVEL_BITS_1_BYTE (UART_FIFO_TF_LEVEL_VALUE_1_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_2_BYTE 2U -#define UART_FIFO_TF_LEVEL_BITS_2_BYTE (UART_FIFO_TF_LEVEL_VALUE_2_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_3_BYTE 3U -#define UART_FIFO_TF_LEVEL_BITS_3_BYTE (UART_FIFO_TF_LEVEL_VALUE_3_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_4_BYTE 4U -#define UART_FIFO_TF_LEVEL_BITS_4_BYTE (UART_FIFO_TF_LEVEL_VALUE_4_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_5_BYTE 5U -#define UART_FIFO_TF_LEVEL_BITS_5_BYTE (UART_FIFO_TF_LEVEL_VALUE_5_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_6_BYTE 6U -#define UART_FIFO_TF_LEVEL_BITS_6_BYTE (UART_FIFO_TF_LEVEL_VALUE_6_BYTE << UART_FIFO_TF_LEVEL_SHIFT) -#define UART_FIFO_TF_LEVEL_VALUE_7_BYTE 7U -#define UART_FIFO_TF_LEVEL_BITS_7_BYTE (UART_FIFO_TF_LEVEL_VALUE_7_BYTE << UART_FIFO_TF_LEVEL_SHIFT) - -#define UART_FIFO_RF_CLR_SHIFT 6 -#define UART_FIFO_RF_CLR_WIDTH 1 -#define UART_FIFO_RF_CLR_MASK (((1U << UART_FIFO_RF_CLR_WIDTH) - 1U) << UART_FIFO_RF_CLR_SHIFT) -#define UART_FIFO_RF_CLR_VALUE_DISABLE 0U -#define UART_FIFO_RF_CLR_BITS_DISABLE (UART_FIFO_RF_CLR_VALUE_DISABLE << UART_FIFO_RF_CLR_SHIFT) -#define UART_FIFO_RF_CLR_VALUE_ENABLE 1U -#define UART_FIFO_RF_CLR_BITS_ENABLE (UART_FIFO_RF_CLR_VALUE_ENABLE << UART_FIFO_RF_CLR_SHIFT) - -#define UART_FIFO_TF_CLR_SHIFT 7 -#define UART_FIFO_TF_CLR_WIDTH 1 -#define UART_FIFO_TF_CLR_MASK (((1U << UART_FIFO_TF_CLR_WIDTH) - 1U) << UART_FIFO_TF_CLR_SHIFT) -#define UART_FIFO_TF_CLR_VALUE_DISABLE 0U -#define UART_FIFO_TF_CLR_BITS_DISABLE (UART_FIFO_TF_CLR_VALUE_DISABLE << UART_FIFO_TF_CLR_SHIFT) -#define UART_FIFO_TF_CLR_VALUE_ENABLE 1U -#define UART_FIFO_TF_CLR_BITS_ENABLE (UART_FIFO_TF_CLR_VALUE_ENABLE << UART_FIFO_TF_CLR_SHIFT) - -#define UART_FC_CTSEN_SHIFT 0 -#define UART_FC_CTSEN_WIDTH 1 -#define UART_FC_CTSEN_MASK (((1U << UART_FC_CTSEN_WIDTH) - 1U) << UART_FC_CTSEN_SHIFT) -#define UART_FC_CTSEN_VALUE_DISABLE 0U -#define UART_FC_CTSEN_BITS_DISABLE (UART_FC_CTSEN_VALUE_DISABLE << UART_FC_CTSEN_SHIFT) -#define UART_FC_CTSEN_VALUE_ENABLE 1U -#define UART_FC_CTSEN_BITS_ENABLE (UART_FC_CTSEN_VALUE_ENABLE << UART_FC_CTSEN_SHIFT) - -#define UART_FC_RTSEN_SHIFT 1 -#define UART_FC_RTSEN_WIDTH 1 -#define UART_FC_RTSEN_MASK (((1U << UART_FC_RTSEN_WIDTH) - 1U) << UART_FC_RTSEN_SHIFT) -#define UART_FC_RTSEN_VALUE_DISABLE 0U -#define UART_FC_RTSEN_BITS_DISABLE (UART_FC_RTSEN_VALUE_DISABLE << UART_FC_RTSEN_SHIFT) -#define UART_FC_RTSEN_VALUE_ENABLE 1U -#define UART_FC_RTSEN_BITS_ENABLE (UART_FC_RTSEN_VALUE_ENABLE << UART_FC_RTSEN_SHIFT) - -#define UART_FC_CTSPOL_SHIFT 2 -#define UART_FC_CTSPOL_WIDTH 1 -#define UART_FC_CTSPOL_MASK (((1U << UART_FC_CTSPOL_WIDTH) - 1U) << UART_FC_CTSPOL_SHIFT) -#define UART_FC_CTSPOL_VALUE_LOW 0U -#define UART_FC_CTSPOL_BITS_LOW (UART_FC_CTSPOL_VALUE_LOW << UART_FC_CTSPOL_SHIFT) -#define UART_FC_CTSPOL_VALUE_HIGH 1U -#define UART_FC_CTSPOL_BITS_HIGH (UART_FC_CTSPOL_VALUE_HIGH << UART_FC_CTSPOL_SHIFT) - -#define UART_FC_RTSPOL_SHIFT 3 -#define UART_FC_RTSPOL_WIDTH 1 -#define UART_FC_RTSPOL_MASK (((1U << UART_FC_RTSPOL_WIDTH) - 1U) << UART_FC_RTSPOL_SHIFT) -#define UART_FC_RTSPOL_VALUE_LOW 0U -#define UART_FC_RTSPOL_BITS_LOW (UART_FC_RTSPOL_VALUE_LOW << UART_FC_RTSPOL_SHIFT) -#define UART_FC_RTSPOL_VALUE_HIGH 1U -#define UART_FC_RTSPOL_BITS_HIGH (UART_FC_RTSPOL_VALUE_HIGH << UART_FC_RTSPOL_SHIFT) - -#define UART_FC_CTS_SIGNAL_SHIFT 4 -#define UART_FC_CTS_SIGNAL_WIDTH 1 -#define UART_FC_CTS_SIGNAL_MASK (((1U << UART_FC_CTS_SIGNAL_WIDTH) - 1U) << UART_FC_CTS_SIGNAL_SHIFT) -#define UART_FC_CTS_SIGNAL_VALUE_LOW 0U -#define UART_FC_CTS_SIGNAL_BITS_LOW (UART_FC_CTS_SIGNAL_VALUE_LOW << UART_FC_CTS_SIGNAL_SHIFT) -#define UART_FC_CTS_SIGNAL_VALUE_HIGH 1U -#define UART_FC_CTS_SIGNAL_BITS_HIGH (UART_FC_CTS_SIGNAL_VALUE_HIGH << UART_FC_CTS_SIGNAL_SHIFT) - -#define UART_FC_RTS_SIGNAL_SHIFT 5 -#define UART_FC_RTS_SIGNAL_WIDTH 1 -#define UART_FC_RTS_SIGNAL_MASK (((1U << UART_FC_RTS_SIGNAL_WIDTH) - 1U) << UART_FC_RTS_SIGNAL_SHIFT) -#define UART_FC_RTS_SIGNAL_VALUE_LOW 0U -#define UART_FC_RTS_SIGNAL_BITS_LOW (UART_FC_RTS_SIGNAL_VALUE_LOW << UART_FC_RTS_SIGNAL_SHIFT) -#define UART_FC_RTS_SIGNAL_VALUE_HIGH 1U -#define UART_FC_RTS_SIGNAL_BITS_HIGH (UART_FC_RTS_SIGNAL_VALUE_HIGH << UART_FC_RTS_SIGNAL_SHIFT) - - -#endif - diff --git a/App/driver/flash.h b/App/driver/flash.h index b827c4c5..fe5ab6e8 100644 --- a/App/driver/flash.h +++ b/App/driver/flash.h @@ -17,36 +17,34 @@ #ifndef DRIVER_FLASH_H #define DRIVER_FLASH_H -#include "bsp/dp32g030/flash.h" - enum FLASH_READ_MODE { - FLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_VALUE_1_CYCLE, - FLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_VALUE_2_CYCLE, + FLASH_READ_MODE_1_CYCLE, // FLASH_CFG_READ_MD_VALUE_1_CYCLE, + FLASH_READ_MODE_2_CYCLE, // FLASH_CFG_READ_MD_VALUE_2_CYCLE, }; typedef enum FLASH_READ_MODE FLASH_READ_MODE; enum FLASH_MASK_SELECTION { - FLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_VALUE_NONE, - FLASH_MASK_SELECTION_2KB = FLASH_MASK_SEL_VALUE_2KB, - FLASH_MASK_SELECTION_4KB = FLASH_MASK_SEL_VALUE_4KB, - FLASH_MASK_SELECTION_8KB = FLASH_MASK_SEL_VALUE_8KB, + FLASH_MASK_SELECTION_NONE, // FLASH_MASK_SEL_VALUE_NONE, + FLASH_MASK_SELECTION_2KB , // FLASH_MASK_SEL_VALUE_2KB, + FLASH_MASK_SELECTION_4KB , // FLASH_MASK_SEL_VALUE_4KB, + FLASH_MASK_SELECTION_8KB , // FLASH_MASK_SEL_VALUE_8KB, }; typedef enum FLASH_MASK_SELECTION FLASH_MASK_SELECTION; enum FLASH_MODE { - FLASH_MODE_READ_AHB = FLASH_CFG_MODE_VALUE_READ_AHB, - FLASH_MODE_PROGRAM = FLASH_CFG_MODE_VALUE_PROGRAM, - FLASH_MODE_ERASE = FLASH_CFG_MODE_VALUE_ERASE, - FLASH_MODE_READ_APB = FLASH_CFG_MODE_VALUE_READ_APB, + FLASH_MODE_READ_AHB, // FLASH_CFG_MODE_VALUE_READ_AHB, + FLASH_MODE_PROGRAM , // FLASH_CFG_MODE_VALUE_PROGRAM, + FLASH_MODE_ERASE , // FLASH_CFG_MODE_VALUE_ERASE, + FLASH_MODE_READ_APB, // FLASH_CFG_MODE_VALUE_READ_APB, }; typedef enum FLASH_MODE FLASH_MODE; enum FLASH_AREA { - FLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_VALUE_MAIN, - FLASH_AREA_NVR = FLASH_CFG_NVR_SEL_VALUE_NVR, + FLASH_AREA_MAIN, // FLASH_CFG_NVR_SEL_VALUE_MAIN, + FLASH_AREA_NVR , // FLASH_CFG_NVR_SEL_VALUE_NVR, }; typedef enum FLASH_AREA FLASH_AREA; diff --git a/App/firmware.ld b/App/firmware.ld deleted file mode 100644 index a7bd16bb..00000000 --- a/App/firmware.ld +++ /dev/null @@ -1,79 +0,0 @@ -ENTRY(HandlerReset) - -_estack = 0x20004000; /* end of 16K RAM */ - -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0x80; /* required amount of stack */ - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 60K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K -} - -SECTIONS -{ - /* Program code */ - .text : - { - . = ALIGN(4); - KEEP(*(.text.isr)) /* .text sections of code */ - *(.text) /* .text sections of code */ - *(.text*) /* .text* sections of code */ - *(.rodata) /* .rodata sections */ - *(.rodata*) /* .rodata* sections */ - *(.glue_7) /* Glue arm to thumb code */ - *(.glue_7t) /* Glue thumb to arm code */ - *(.eh_frame) - - KEEP(*(.fini)) - . = ALIGN(4); - _etext = .; /* global symbols at end */ - } >FLASH - - /* Used by startup code */ - - . = ALIGN(4); - - flash_data_start = .; - - .data : - { - . = ALIGN(4); - sram_data_start = .; - *(.sramtext) - *(.srambss) - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* Global symbol at data end */ - } >RAM AT> FLASH - - sram_data_end = .; - - /* Uninitialized data */ - . = ALIGN(4); - .bss : - { - _sbss = .; /* Global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* Global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* Check that there is enough RAM */ - ._user_heap_stack : - { - . = ALIGN(4); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM -} - diff --git a/App/start.S b/App/start.S deleted file mode 100644 index eb29dd73..00000000 --- a/App/start.S +++ /dev/null @@ -1,253 +0,0 @@ -# Copyright 2023 Dual Tachyon -# https://github.com/DualTachyon -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - - .cpu cortex-m0 - .fpu softvfp - .thumb - - .global Stack - .global HandlerReset - .global Main - - .global OVERLAY_Install - .global BOARD_FLASH_Init - .global BSS_Init - - .global SystickHandler - .weak SystickHandler - - .section .text.isr - -Stack: - .long 0x20003FF0 -Reset: - .long HandlerReset + 1 -NMI: - .long HandlerNMI + 1 -HardFault: - .long HandlerHardFault + 1 -Reserved_10: - .long 0 -Reserved_14: - .long 0 -Reserved_18: - .long 0 -Reserved_1C: - .long 0 -Reserved_20: - .long 0 -Reserved_24: - .long 0 -Reserved_28: - .long 0 -SVCall: - .long HandlerSVCall + 1 -Reserved_30: - .long 0 -Reserved_34: - .long 0 -PendSV: - .long HandlerPendSV + 1 -SysTick: - .long SystickHandler + 1 -WWDT: - .long HandlerWWDT + 1 -IWDT: - .long HandlerIWDT + 1 -RTC: - .long HandlerRTC + 1 -DMA: - .long HandlerDMA + 1 -SARADC: - .long HandlerSARADC + 1 -TIMER_BASE0: - .long HandlerTIMER_BASE0 + 1 -TIMER_BASE1: - .long HandlerTIMER_BASE1 + 1 -TIMER_PLUS0: - .long HandlerTIMER_PLUS0 + 1 -TIMER_PLUS1: - .long HandlerTIMER_PLUS1 + 1 -PWM_BASE0: - .long HandlerPWM_BASE0 + 1 -PWM_BASE1: - .long HandlerPWM_BASE1 + 1 -PWM_PLUS0: - .long HandlerPWM_PLUS0 + 1 -PWM_PLUS1: - .long HandlerPWM_PLUS1 + 1 -UART0: - .long HandlerUART0 + 1 -UART1: - .long HandlerUART1 + 1 -UART2: - .long HandlerUART2 + 1 -SPI0: - .long HandlerSPI0 + 1 -SPI1: - .long HandlerSPI1 + 1 -IIC0: - .long HandlerIIC0 + 1 -IIC1: - .long HandlerIIC1 + 1 -CMP: - .long HandlerCMP + 1 -TIMER_BASE2: - .long HandlerTIMER_BASE2 + 1 -GPIOA5: - .long HandlerGPIOA5 + 1 -GPIOA6: - .long HandlerGPIOA6 + 1 -GPIOA7: - .long HandlerGPIOA7 + 1 -GPIOB0: - .long HandlerGPIOB0 + 1 -GPIOB1: - .long HandlerGPIOB1 + 1 -GPIOC0: - .long HandlerGPIOC0 + 1 -GPIOC1: - .long HandlerGPIOC1 + 1 -GPIOA: - .long HandlerGPIOA + 1 -GPIOB: - .long HandlerGPIOB + 1 -GPIOC: - .long HandlerGPIOC + 1 - - .section .text - -HandlerNMI: - b . - -HandlerHardFault: - b . - -HandlerSVCall: - b . - -HandlerPendSV: - b . - -SystickHandler: - bx lr - -HandlerWWDT: - b . - -HandlerIWDT: - b . - -HandlerRTC: - b . - -HandlerDMA: - b . - -HandlerSARADC: - b . - -HandlerTIMER_BASE0: - b . - -HandlerTIMER_BASE1: - b . - -HandlerTIMER_PLUS0: - b . - -HandlerTIMER_PLUS1: - b . - -HandlerPWM_BASE0: - b . - -HandlerPWM_BASE1: - b . - -HandlerPWM_PLUS0: - b . - -HandlerPWM_PLUS1: - b . - -HandlerUART0: - b . - -HandlerUART1: - b . - -HandlerUART2: - b . - -HandlerSPI0: - b . - -HandlerSPI1: - b . - -HandlerIIC0: - b . - -HandlerIIC1: - b . - -HandlerCMP: - b . - -HandlerTIMER_BASE2: - b . - -HandlerGPIOA5: - b . - -HandlerGPIOA6: - b . - -HandlerGPIOA7: - b . - -HandlerGPIOB0: - b . - -HandlerGPIOB1: - b . - -HandlerGPIOC0: - b . - -HandlerGPIOC1: - b . - -HandlerGPIOA: - b . - -HandlerGPIOB: - b . - -HandlerGPIOC: - b . - -HandlerReset: - ldr r0, =0x20003FF0 - mov sp, r0 - bl DATA_Init - bl BSS_Init -#if defined(ENABLE_OVERLAY) - bl BOARD_FLASH_Init -#endif - bl Main - b . -