mirror of
https://github.com/armel/uv-k1-k5v3-firmware-custom.git
synced 2026-10-02 03:15:37 +00:00
Port K1 drivers
Port drivers: gpio, keyboad, system, systick, uart, flashlight
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@@ -1,4 +1,5 @@
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/* Copyright 2023 Dual Tachyon
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/* Copyright 2025 muzkr https://github.com/muzkr
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* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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@@ -16,73 +17,90 @@
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#include <stdbool.h>
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#include <string.h>
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#include "bsp/dp32g030/dma.h"
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#include "bsp/dp32g030/syscon.h"
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#include "bsp/dp32g030/uart.h"
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#include "py32f071_ll_bus.h"
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#include "py32f071_ll_system.h"
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#include "py32f071_ll_dma.h"
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#include "py32f071_ll_gpio.h"
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#include "py32f071_ll_usart.h"
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#include "driver/uart.h"
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#define _DMA_CHANNEL LL_DMA_CHANNEL_2
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static bool UART_IsLogEnabled;
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uint8_t UART_DMA_Buffer[256];
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void UART_Init(void)
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{
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uint32_t Delta;
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uint32_t Positive;
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uint32_t Frequency;
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// PA9 TX
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// PA10 RX
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UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE;
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Delta = SYSCON_RC_FREQ_DELTA;
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Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;
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Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;
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if (Positive) {
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Frequency += 48000000U;
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} else {
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Frequency = 48000000U - Frequency;
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}
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LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_USART1);
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UART1->BAUD = Frequency / 39053U;
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UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE;
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UART1->RXTO = 4;
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UART1->FC = 0;
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UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE;
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UART1->IE = 0;
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// Pins
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do
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{
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LL_GPIO_InitTypeDef GPIO_InitStruct;
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LL_GPIO_StructInit(&GPIO_InitStruct);
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GPIO_InitStruct.Pin = LL_GPIO_PIN_9 | LL_GPIO_PIN_10;
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GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
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GPIO_InitStruct.Alternate = LL_GPIO_AF1_USART1;
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GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
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DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE;
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LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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} while (0);
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DMA_CH0->MSADDR = (uint32_t)(uintptr_t)&UART1->RDR;
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DMA_CH0->MDADDR = (uint32_t)(uintptr_t)UART_DMA_Buffer;
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DMA_CH0->MOD = 0
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// Source
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| DMA_CH_MOD_MS_ADDMOD_BITS_NONE
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| DMA_CH_MOD_MS_SIZE_BITS_8BIT
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| DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1
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// Destination
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| DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT
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| DMA_CH_MOD_MD_SIZE_BITS_8BIT
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| DMA_CH_MOD_MD_SEL_BITS_SRAM
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;
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DMA_INTEN = 0;
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DMA_INTST = 0
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| DMA_INTST_CH0_TC_INTST_BITS_SET
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| DMA_INTST_CH1_TC_INTST_BITS_SET
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| DMA_INTST_CH2_TC_INTST_BITS_SET
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| DMA_INTST_CH3_TC_INTST_BITS_SET
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| DMA_INTST_CH0_THC_INTST_BITS_SET
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| DMA_INTST_CH1_THC_INTST_BITS_SET
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| DMA_INTST_CH2_THC_INTST_BITS_SET
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| DMA_INTST_CH3_THC_INTST_BITS_SET
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;
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DMA_CH0->CTR = 0
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| DMA_CH_CTR_CH_EN_BITS_ENABLE
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| ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK)
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| DMA_CH_CTR_LOOP_BITS_ENABLE
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| DMA_CH_CTR_PRI_BITS_MEDIUM
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;
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UART1->IF = UART_IF_RXTO_BITS_SET;
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// DMA
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do
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{
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LL_DMA_DisableChannel(DMA1, _DMA_CHANNEL);
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DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_ENABLE;
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LL_DMA_InitTypeDef DMA_InitStruct;
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LL_DMA_StructInit(&DMA_InitStruct);
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UART1->CTRL |= UART_CTRL_UARTEN_BITS_ENABLE;
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DMA_InitStruct.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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DMA_InitStruct.Mode = LL_DMA_MODE_CIRCULAR;
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DMA_InitStruct.PeriphOrM2MSrcAddress = LL_USART_DMA_GetRegAddr(USART1);
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DMA_InitStruct.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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DMA_InitStruct.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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DMA_InitStruct.MemoryOrM2MDstAddress = (uint32_t)UART_DMA_Buffer;
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DMA_InitStruct.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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DMA_InitStruct.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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DMA_InitStruct.NbData = sizeof(UART_DMA_Buffer);
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DMA_InitStruct.Priority = LL_DMA_PRIORITY_HIGH;
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LL_DMA_Init(DMA1, _DMA_CHANNEL, &DMA_InitStruct);
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LL_SYSCFG_SetDMARemap(DMA1, _DMA_CHANNEL, LL_SYSCFG_DMA_MAP_USART1_RD);
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} while (0);
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LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1);
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LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1);
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// USART
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do
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{
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LL_USART_Disable(USART1);
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LL_USART_InitTypeDef USART_InitStruct;
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LL_USART_StructInit(&USART_InitStruct);
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USART_InitStruct.BaudRate = 38400;
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USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
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LL_USART_Init(USART1, &USART_InitStruct);
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LL_USART_EnableDMAReq_RX(USART1);
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} while (0);
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LL_DMA_EnableChannel(DMA1, _DMA_CHANNEL);
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LL_USART_Enable(USART1);
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LL_USART_TransmitData8(USART1, 0);
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}
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void UART_Send(const void *pBuffer, uint32_t Size)
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@@ -90,10 +108,11 @@ void UART_Send(const void *pBuffer, uint32_t Size)
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const uint8_t *pData = (const uint8_t *)pBuffer;
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uint32_t i;
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for (i = 0; i < Size; i++) {
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UART1->TDR = pData[i];
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while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_BITS_NOT_SET) {
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}
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for (i = 0; i < Size; i++)
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{
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while (!LL_USART_IsActiveFlag_TXE(USART1))
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;
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LL_USART_TransmitData8(USART1, pData[i]);
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}
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}
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