mckero/uv-k1-k5v3-firmware-custom
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Add SetCfg to pick a config bank independently of the slot

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Armel FAUVEAU committed 2026-08-21 02:56:54 +02:00
1 parent 5b6174085b
commit e4a645a5c7
12 files changed
+502 -243
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App/driver/py25q16.h
+15 -13
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@@ -27,33 +27,35 @@ void PY25Q16_WriteBuffer(uint32_t Address, const void *pBuffer, uint32_t Size, b
void PY25Q16_SectorErase(uint32_t Address);
/* Drop the internal single-sector write cache. Call after erasing/programming
* flash behind the driver's back (e.g. the raw multiboot slot/profile ops) so a
* flash behind the driver's back (e.g. the raw multiboot slot/bank ops) so a
* later write cannot skip or resurrect data based on a stale cached sector. It
* is also called before multiboot reuses the cache storage as a RAM overlay. */
void PY25Q16_InvalidateCache(void);
#ifdef ENABLE_FEAT_F4HWN_MULTIBOOT
/*
* Multiboot per-profile config banking.
* Multiboot per-bank config banking.
*
* Each firmware slot owns a private copy of the user configuration (memory
* channels, names, VFOs, settings). A non-zero profile base transparently
* shifts every flash access BELOW PY25Q16_PROFILE_SHARED_FROM into the active
* profile's bank; calibration, boot logo, firmware slots and the multiboot
* marker all live at/above that boundary and stay shared across every profile.
* Each firmware slot gets its own config bank by default (memory channels,
* names, VFOs, settings), though SetCfg can point the running firmware at a
* different bank. A non-zero bank base transparently shifts every flash access
* BELOW PY25Q16_BANK_SHARED_FROM into the active bank; calibration, boot logo,
* firmware slots and the multiboot marker all live at/above that boundary and
* stay shared across every bank.
*
* This is the single choke point: both the EEPROM emulation (eeprom_compat.c)
* and the firmware's direct config reads/writes (settings.c) end up here, so
* one offset covers them all - no per-call-site patching.
*
* Set once at boot, before any settings read, from
* PY25Q16_SetProfileBase(MB_ProfileBase(MB_BootResolveProfile()));
* and never changed again during a session (the profile only changes through a
* reflash + reset), so the banking itself never needs a cache flush. Raw profile
* erases behind the driver explicitly call PY25Q16_InvalidateCache().
* PY25Q16_SetBankBase(MB_BankBase(MB_BootResolveState()));
* and never changed again during a session (a slot restore or SetCfg selection
* records the next bank and resets first), so the banking itself never needs a
* cache flush. Raw bank erases behind the driver explicitly call
* PY25Q16_InvalidateCache().
*/
#define PY25Q16_PROFILE_SHARED_FROM 0x00010000u /* calibration boundary (see flash map) */
void PY25Q16_SetProfileBase(uint32_t Base);
#define PY25Q16_BANK_SHARED_FROM 0x00010000u /* calibration boundary (see flash map) */
void PY25Q16_SetBankBase(uint32_t Base);
#endif
#endif