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@@ -0,0 +1,22 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
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# debugger/programmer
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#
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# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect"
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# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect"
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#
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# SWIM transport is natively supported
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#
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adapter driver st-link
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st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
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# transport select dapdirect_jtag
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# transport select dapdirect_swd
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# transport select swim
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# Optionally specify the serial number of usb device
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# e.g.
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# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
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@@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg"
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source [find interface/stlink.cfg]
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@@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg"
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source [find interface/stlink.cfg]
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@@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg"
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source [find interface/stlink.cfg]
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@@ -0,0 +1,18 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
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# debugger/programmer
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#
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adapter driver hla
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hla layout stlink
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hla device_desc "ST-LINK"
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hla vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
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# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
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# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
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# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
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# number reset issues.
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# eg.
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#adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
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@@ -0,0 +1,359 @@
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#OpenOCD script for Action Dynamic DP32G030 ARM Cortex M0 CPU (UV-5R, UV-k5 Ham HTs)
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#For use with cheap ST-Link USB debug probe
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source target/swj-dp.tcl
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set _CHIP_NAME DP32G0xx
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set _ENDIAN little
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set _WORKAREASIZE 0x1000
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set _FLASH_SIZE 0x10000
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set _CPUTAPID 0x0BB11477
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set _TARGETNAME $_CHIP_NAME.cpu
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set _FLASHNAME $_CHIP_NAME.flash
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set _SECTOR_SIZE 512
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set _MASKING_CFG 2 ;#1:2kB, 2:4kB, 3:8kB
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adapter speed 960
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adapter srst delay 100
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reset_config srst_nogate
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# Create a new dap, with name chip and role CPU, -enable let's OpenOCD to know to add it to the scan
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swj_newdap $_CHIP_NAME cpu -expected-id $_CPUTAPID -enable
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# Create the DAP instance, this must be explicitly created according to the OpenOCD docs
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dap create $_CHIP_NAME.dap -chain-position $_CHIP_NAME.cpu
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# Set up the GDB target for the CPU
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target create $_CHIP_NAME.cpu cortex_m -endian $_ENDIAN -dap $_CHIP_NAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# Declare internal bank
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flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
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proc check_readiness {} {
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while {[read_memory 0x4006F014 32 1] & 0x2} {}
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}
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proc rom_mask_off {} {
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echo "\nChecking ROM masking"
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check_readiness
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set status [read_memory 0x4006F020 32 1]
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if {($status & 0x3) != 0} {
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echo [format "\nROM masking is set to 0b%03b. Unsetting..." $status]
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write_memory 0x4006F020 32 [expr {[read_memory 0x4006F020 32 1] & 0x3}]
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check_readiness
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write_memory 0x4006F020 32 0
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check_readiness
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write_memory 0x4006F020 32 4
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}
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return [read_memory 0x4006F020 32 1]
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}
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proc rom_mask_on {} {
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global _MASKING_CFG
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echo "\nChecking ROM masking"
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check_readiness
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set status [read_memory 0x4006F020 32 1]
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if {($status & 0x3) != $_MASKING_CFG} {
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echo [format "\nROM masking is set to 0b%03b. Setting ON..." $status]
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write_memory 0x4006F020 32 [expr {[read_memory 0x4006F020 32 1] & 0x3}]
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check_readiness
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write_memory 0x4006F020 32 $_MASKING_CFG
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check_readiness
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write_memory 0x4006F020 32 [expr {4 | $_MASKING_CFG}]
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}
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return [read_memory 0x4006F020 32 1]
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}
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proc unlock_rom {} {
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write_memory 0x4006F01c 32 0xAA
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check_readiness
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}
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proc lock_rom {} {
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write_memory 0x4006F018 32 0x55
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check_readiness
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}
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proc select_region {target_r} {
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#Region 0 is main user ROM area, 1 is NVRAM area
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write_memory 0x4006F000 32 [expr {(0x31 & [read_memory 0x4006F000 32 1]) | (($target_r & 0x1) << 1)}]
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check_readiness
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}
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proc wipe_sector_range {st_sec sec_count} {
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set last [expr {$st_sec + $sec_count}]
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set reg [expr {[read_memory 0x4006F000 32 1] & 0x7FFFFFFF}]
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write_memory 0x4006F000 32 [expr {$reg | 0x8}] ;#set writing mode ERASE
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for {set i $st_sec} {$i < $last} {incr i} {
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check_readiness
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echo -n [format "\rErasing sector 0x%02x = offset 0x%04x" [expr {$i}] [expr {$i*512}] ]
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write_memory 0x4006F004 32 [expr {$i << 7}] ;#set address in flash
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write_memory 0x4006F010 32 0x01 ;#do it
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}
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check_readiness
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write_memory 0x4006F000 32 $reg
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}
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proc wipe_rom {} {
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#This will wipe everything including bootloader
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global _SECTOR_SIZE
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global _FLASH_SIZE
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unlock_rom
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select_region 0
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if {[rom_mask_off] != 4} {
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echo "\nROM Masking failed to disable!"
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close $fd
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return
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}
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wipe_sector_range 0 [expr {$_FLASH_SIZE / $_SECTOR_SIZE}]
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}
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proc binary_to_int {data} {
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# Complète la chaîne à 4 octets si nécessaire
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set data $data[string repeat \xFF [expr {4 - [string length $data]}]]
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# Initialise le résultat à 0
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set result 0
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# Parcourt les octets et assemble l'entier
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for {set i 0} {$i < 4} {incr i} {
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# Récupère l'octet à la position $i
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set byte [scan [string index $data $i] %c]
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# Décale l'octet en fonction de l'ordre Little Endian
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set result [expr {$result | ($byte & 0xFF) << (8 * $i)}]
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}
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return $result
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}
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proc write_image {filename offset} {
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global _SECTOR_SIZE
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global _FLASH_SIZE
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set fs [file size $filename]
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set fd [open $filename "rb"]
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set reg [expr {[read_memory 0x4006F000 32 1] & 0x7FFFFFFF}]
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write_memory 0x4006F000 32 [expr {$reg | 0x4}] ;#set writing mode PROGRAM
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while {![eof $fd]} {
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if {($offset+4) > $_FLASH_SIZE} {
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echo "\nData exceeds main storage capacity!"
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write_memory 0x4006F000 32 $reg
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lock_rom
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close $fd
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return
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}
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check_readiness
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set data [read $fd 4]
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set data $data[string repeat \xFF [expr {4-[string length $data]}]] ;#padding
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#binary scan $data i i_data
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set i_data [binary_to_int $data]
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write_memory 0x4006F004 32 [expr {($offset>>2)+0xC000}] ;#set destination offset
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write_memory 0x4006F008 32 $i_data ;#set word
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write_memory 0x4006F010 32 0x01 ;#set OPSTART=1
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while {([read_memory 0x4006F014 32 1] & 4) == 0} {}
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echo -n [format "\rProgrammed up to 0x%04x (FLASH_ADDR=0x%04x)" $offset [expr {($offset>>2)+0xC000}]]
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incr offset 4
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}
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check_readiness
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write_memory 0x4006F000 32 $reg ;#reset writing mode to OFF
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}
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proc flash_blocks {filename address nblocks offset} {
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#Intended for speed. Due to tight timings, sometimes it works, sometimes it does not. Needs clocks adjusting there.
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global _SECTOR_SIZE
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global _FLASH_SIZE
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if {($nblocks != 0) & [expr {$nblocks & 1}]} {
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set nblocks [expr {$nblocks + 1}]
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}
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set addr [expr {$_SECTOR_SIZE * ($address >> 9)}]
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set fs [expr {((($_SECTOR_SIZE*$nblocks)/2 + $_SECTOR_SIZE-1)&(0x10000000-$_SECTOR_SIZE))}]
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set fd [open $filename "rb"]
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read $fd $addr
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set addr [expr {$addr + $offset}] ;#apply ROM offset
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set reg [expr {[read_memory 0x4006F000 32 1] & 0x7FFFFFFF}]
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echo -n [format "\tWiping %02d sectors, starting at %02d " [expr {$nblocks / 2}] [expr {$addr >> 9}]]
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wipe_sector_range [expr {$addr >> 9}] [expr {$nblocks / 2}] ;#wipe related sectors
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echo "\nRegion cleared OK"
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echo [format "%02d bytes to push" $fs]; ##DEBUG
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write_memory 0x4006F000 32 [expr {$reg | 0x4}] ;#set writing mode PROGRAM
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while {$fs > 0} {
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write_memory 0x4006F004 32 [expr {0xC000+(($addr)>>2)}] ;#set block starting offset
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set i_buffer {}
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for {set blk 0} {$blk < $_SECTOR_SIZE/2} {incr blk 4} {
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set data [read $fd 4]
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set data $data[string repeat \xFF [expr {4-[string length $data]}]] ;#padding to desired ending block
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if {($addr+$_SECTOR_SIZE/2) >= $_FLASH_SIZE} {
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echo [format "\nMain firmware image upper boundary reached (%d)!" $addr]
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write_memory 0x4006F000 32 $reg ;#reset writing mode to OFF
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close $fd
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return
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}
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binary scan $data i i_data
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lappend i_buffer [expr {$i_data & 0xFFFFFFFF}]
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incr fs -4
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}
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echo [format "\nWriting at offset 0x%04x" [expr {$addr}]]
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##for {set bi 0} {$bi < 64} {incr bi} {echo -n [format "%08x" [lindex $i_buffer $bi]]}; #DEBUG
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write_memory 0x4006F008 32 [lindex $i_buffer 0] ;#prepare 1st word: we need to be quick beyond this point
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check_readiness
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write_memory 0x4006F010 32 0x01
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for {set bi 1} {$bi < 64} {incr bi} {while {([read_memory 0x4006F014 32 1] & 0x4) == 4} {write_memory 0x4006F008 32 [lindex $i_buffer $bi]}}
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check_readiness
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incr addr $_SECTOR_SIZE/2 ;# Next block
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}
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write_memory 0x4006F000 32 $reg ;#reset writing mode to OFF
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echo [format "\nLast write was 0x%08x " [lindex $i_buffer 63]]
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close $fd
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return
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}
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proc toggle_pin_gpioa {pin} {
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write_memory 0x40060000 16 [expr {[read_memory 0x40060000 16 1] ^(1<<$pin) }]
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}
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proc toggle_pin_gpiob {pin} {
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write_memory 0x40060800 16 [expr {[read_memory 0x40060800 16 1] ^(1<<$pin) }]
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}
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proc toggle_pin_gpioc {pin} {
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write_memory 0x40061000 16 [expr {[read_memory 0x40061000 16 1] ^(1<<$pin) }]
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}
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proc set_pin_gpioa {pin value} {
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if {$value == 0} {
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write_memory 0x40060000 16 [expr {[read_memory 0x40060000 16 1] &~(1<<$pin) }]
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} else {
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write_memory 0x40060000 16 [expr {[read_memory 0x40060000 16 1] |(1<<$pin) }]
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}
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}
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proc set_pin_gpiob {pin value} {
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if {$value == 0} {
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write_memory 0x40060800 16 [expr {[read_memory 0x40060800 16 1] &~(1<<$pin) }]
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} else {
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write_memory 0x40060800 16 [expr {[read_memory 0x40060800 16 1] |(1<<$pin) }]
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}
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}
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proc set_pin_gpioc {pin value} {
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if {$value == 0} {
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write_memory 0x40061000 16 [expr {[read_memory 0x40061000 16 1] &~(1<<$pin) }]
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} else {
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write_memory 0x40061000 16 [expr {[read_memory 0x40061000 16 1] |(1<<$pin) }]
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}
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}
|
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|
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##Quansheng UVK5-specific snippets
|
||||
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proc uv_fastflash_bl {filename} {
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write_memory 0x4006F024 32 0x4E02A300 ;#force stock timings, just in case
|
||||
write_memory 0x4006F028 32 0x210360
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write_memory 0x4006F000 32 0x1
|
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check_readiness
|
||||
select_region 0
|
||||
if {[rom_mask_off] != 4} {
|
||||
echo "\nROM Masking failed to disable!"
|
||||
close $fd
|
||||
return
|
||||
}
|
||||
reset halt
|
||||
unlock_rom
|
||||
|
||||
flash_blocks $filename 0 16 0
|
||||
|
||||
#just relock flashROM
|
||||
lock_rom
|
||||
}
|
||||
|
||||
proc uv_fastflash_fw {filename} {
|
||||
#Make sure bootloader is hidden
|
||||
if {[rom_mask_on] != 6} {
|
||||
echo "\nROM Masking failed to enable!"
|
||||
close $fd
|
||||
return
|
||||
}
|
||||
reset halt
|
||||
unlock_rom
|
||||
|
||||
flash_blocks $filename 0 [expr {[file size $filename] >> 8}] 0
|
||||
reset
|
||||
echo "\nCPU reset: Transceiver should boot now."
|
||||
}
|
||||
|
||||
proc uv_flash_bl {filename} {
|
||||
#Securely rewrites bootloader (slowly)
|
||||
|
||||
if {[file size $filename] > 0x1000} {
|
||||
echo [format "Bootloader image is too large to fit!]
|
||||
return
|
||||
}
|
||||
select_region 0
|
||||
if {[rom_mask_off] != 4} {
|
||||
echo "\nROM Masking failed to disable!"
|
||||
return
|
||||
}
|
||||
reset halt
|
||||
unlock_rom
|
||||
|
||||
wipe_sector_range 0 8
|
||||
echo "\nRegion cleared OK"
|
||||
|
||||
write_image $filename 0
|
||||
|
||||
if {[rom_mask_on] != 6} {
|
||||
echo "\nROM Masking failed to enable!"
|
||||
lock_rom
|
||||
return
|
||||
}
|
||||
#relock flashROM, in case conventional method for fw is preferred
|
||||
lock_rom
|
||||
echo "\nBootloader code programmed.\nYou can use uv_flash_fw to program main firmware, or just use stock tool to do it."
|
||||
}
|
||||
|
||||
proc uv_flash_fw {filename} {
|
||||
#Securely rewrites main firmware (slowly)
|
||||
|
||||
select_region 0
|
||||
#Make sure bootloader is hidden
|
||||
if {[rom_mask_on] != 6} {
|
||||
echo "\nROM Masking failed to enable!"
|
||||
return
|
||||
}
|
||||
reset halt
|
||||
unlock_rom
|
||||
|
||||
wipe_sector_range 0 120
|
||||
echo "\nRegion cleared OK"
|
||||
|
||||
write_image $filename 0
|
||||
|
||||
#relock flashROM, then reset CPU
|
||||
lock_rom
|
||||
reset
|
||||
echo "\nCPU reset: Transceiver should boot now."
|
||||
}
|
||||
|
||||
proc uv_flashlight_toggle {} {
|
||||
toggle_pin_gpioc 3 ;# toggles PORTC.3
|
||||
}
|
||||
|
||||
proc uv_flashlight_on {} {
|
||||
set_pin_gpioc 3 1 ;# set PORTC.3 high
|
||||
}
|
||||
|
||||
proc uv_flashlight_off {} {
|
||||
set_pin_gpioc 3 0 ;# set PORTC.3 to low
|
||||
}
|
||||
|
||||
proc uv_backlight_toggle {} {
|
||||
toggle_pin_gpiob 6 ;# toggles PORTB.6
|
||||
}
|
||||
|
||||
init
|
||||
#reset halt
|
||||
@@ -0,0 +1,34 @@
|
||||
# ARM Debug Interface V5 (ADI_V5) utility
|
||||
# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
|
||||
# SW-DP and JTAG-DP targets don't need to switch based
|
||||
# on which transport is active.
|
||||
#
|
||||
# declare a JTAG or SWD Debug Access Point (DAP)
|
||||
# based on the transport in use with this session.
|
||||
# You can't access JTAG ops when SWD is active, etc.
|
||||
|
||||
# params are currently what "jtag newtap" uses
|
||||
# because OpenOCD internals are still strongly biased
|
||||
# to JTAG .... but for SWD, "irlen" etc are ignored,
|
||||
# and the internals work differently
|
||||
|
||||
# for now, ignore non-JTAG and non-SWD transports
|
||||
# (e.g. initial flash programming via SPI or UART)
|
||||
|
||||
# split out "chip" and "tag" so we can someday handle
|
||||
# them more uniformly irlen too...)
|
||||
|
||||
if [catch {transport select}] {
|
||||
echo "Error: unable to select a session transport. Can't continue."
|
||||
shutdown
|
||||
}
|
||||
|
||||
proc swj_newdap {chip tag args} {
|
||||
if [using_hla] {
|
||||
eval hla newtap $chip $tag $args
|
||||
} elseif [using_jtag] {
|
||||
eval jtag newtap $chip $tag $args
|
||||
} elseif [using_swd] {
|
||||
eval swd newdap $chip $tag $args
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
# ARM Debug Interface V5 (ADI_V5) utility
|
||||
# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
|
||||
# SW-DP and JTAG-DP targets don't need to switch based
|
||||
# on which transport is active.
|
||||
#
|
||||
# declare a JTAG or SWD Debug Access Point (DAP)
|
||||
# based on the transport in use with this session.
|
||||
# You can't access JTAG ops when SWD is active, etc.
|
||||
|
||||
# params are currently what "jtag newtap" uses
|
||||
# because OpenOCD internals are still strongly biased
|
||||
# to JTAG .... but for SWD, "irlen" etc are ignored,
|
||||
# and the internals work differently
|
||||
|
||||
# for now, ignore non-JTAG and non-SWD transports
|
||||
# (e.g. initial flash programming via SPI or UART)
|
||||
|
||||
# split out "chip" and "tag" so we can someday handle
|
||||
# them more uniformly irlen too...)
|
||||
|
||||
if [catch {transport select}] {
|
||||
echo "Error: unable to select a session transport. Can't continue."
|
||||
shutdown
|
||||
}
|
||||
|
||||
proc swj_newdap {chip tag args} {
|
||||
if [using_jtag] {
|
||||
eval jtag newtap $chip $tag $args
|
||||
} elseif [using_swd] {
|
||||
eval swd newdap $chip $tag $args
|
||||
} else {
|
||||
echo "Error: transport '[ transport select ]' not supported by swj_newdap"
|
||||
shutdown
|
||||
}
|
||||
}
|
||||
Executable
+2
@@ -0,0 +1,2 @@
|
||||
#!/usr/bin/env bash
|
||||
openocd -f ./interface/stlink.cfg -f ./target/dp32g030.cfg -c "init; reset halt; uv_flash_bl bootloader.bin; shutdown"
|
||||
Reference in new issue
Block a user